From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-182.mta0.migadu.com (out-182.mta0.migadu.com [91.218.175.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 817532F363E for ; Wed, 31 Dec 2025 02:29:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.182 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767148186; cv=none; b=EYNPFMBmA0m34WqQZV52S+eSf9Er21tHhuCibH7NKz10saI0++CL/DppMnYd2VKfBTKEvW0DHILkJVy0TdQMoHfzT/+G489bxnYZ7trDbIT0LHtRZ3ntx8QLZfs/XVEaBKhBU4pkE7b6KbksnaHBKW/uLv6gz1emVBKaC9BpvcU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767148186; c=relaxed/simple; bh=7rXjqJR/SeOtUouPwaConEb1plJhkxgMWyk7kIs0yws=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=qVeS2W1o3ut5BNXxQQC4UURHbI/16LjwFZ9YlHTM+1mQV33fKvrEL4JuCyyNVuUILSdAHS9GTxf48TBTGjB9S3WZAqglMaEoielf2eqfIOKS2A6ooo6XBG/DLtZtO5tuVk663U/ldixEwWTX42wUS4VhSHmjOJ0c1IZrSHXI+AY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=XWjmBNlf; arc=none smtp.client-ip=91.218.175.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="XWjmBNlf" Message-ID: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1767148180; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=37nD/3cQoIBI0/8IexFOw2YpceIM7p2wvl3IFIN7jQc=; b=XWjmBNlfSH4f7yYWlEW51gqh/6yRLbDw2YvyaNBHRcNpxz64Ud8N5126J65U7ERVSnQQfr 59jIGP68fKaJXi4HB2xgjLejyEflrzDJT8yqvo2Xzz5i73aE1om/wwQUGbnV2tYXPzjyTx xbZc/lV026OlxMR2SGFTkWLyaXCHkQo= Date: Wed, 31 Dec 2025 10:29:29 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH v2 1/3] mm/tlb: allow architectures to skip redundant TLB sync IPIs Content-Language: en-US To: "David Hildenbrand (Red Hat)" , akpm@linux-foundation.org Cc: will@kernel.org, aneesh.kumar@kernel.org, npiggin@gmail.com, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, arnd@arndb.de, lorenzo.stoakes@oracle.com, ziy@nvidia.com, baolin.wang@linux.alibaba.com, Liam.Howlett@oracle.com, npache@redhat.com, ryan.roberts@arm.com, dev.jain@arm.com, baohua@kernel.org, ioworker0@gmail.com, shy828301@gmail.com, riel@surriel.com, jannh@google.com, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org References: <20251229145245.85452-1-lance.yang@linux.dev> <20251229145245.85452-2-lance.yang@linux.dev> <725b85bf-ff5e-45d6-991e-d92598779f98@kernel.org> X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Lance Yang In-Reply-To: <725b85bf-ff5e-45d6-991e-d92598779f98@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT On 2025/12/31 04:31, David Hildenbrand (Red Hat) wrote: > On 12/29/25 15:52, Lance Yang wrote: >> From: Lance Yang >> >> When unsharing hugetlb PMD page tables, we currently send two IPIs: one >> for TLB invalidation, and another to synchronize with concurrent GUP-fast >> walkers. >> >> However, if the TLB flush already reaches all CPUs, the second IPI is >> redundant. GUP-fast runs with IRQs disabled, so when the TLB flush IPI >> completes, any concurrent GUP-fast must have finished. >> >> Add tlb_table_flush_implies_ipi_broadcast() to let architectures indicate >> their TLB flush provides full synchronization, enabling the redundant IPI >> to be skipped. >> >> Suggested-by: David Hildenbrand (Red Hat) >> Signed-off-by: Lance Yang >> --- >>   include/asm-generic/tlb.h | 14 ++++++++++++++ >>   1 file changed, 14 insertions(+) >> >> diff --git a/include/asm-generic/tlb.h b/include/asm-generic/tlb.h >> index 4d679d2a206b..e8d99b5e831f 100644 >> --- a/include/asm-generic/tlb.h >> +++ b/include/asm-generic/tlb.h >> @@ -261,6 +261,20 @@ static inline void >> tlb_remove_table_sync_one(void) { } >>   #endif /* CONFIG_MMU_GATHER_RCU_TABLE_FREE */ >> +/* >> + * Architectures can override if their TLB flush already broadcasts >> IPIs to all >> + * CPUs when freeing or unsharing page tables. >> + * >> + * Return true only when the flush guarantees: >> + * - IPIs reach all CPUs with potentially stale paging-structure >> cache entries >> + * - Synchronization with IRQ-disabled code like GUP-fast >> + */ >> +#ifndef tlb_table_flush_implies_ipi_broadcast >> +static inline bool tlb_table_flush_implies_ipi_broadcast(void) >> +{ >> +    return false; >> +} >> +#endif >>   #ifndef CONFIG_MMU_GATHER_NO_GATHER >>   /* > > > This should likely get squashed into patch #3. Patch #1 itself does not > add a lot of value to be had separately. > > So best to squash both and have them as #1, to then implement it in #2 > for x86. Sounds good, will do! Squashing #1 and #3 together, keeping the x86 implementation as #2 ;) Cheers, Lance