From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 060353FF8B1 for ; Fri, 8 May 2026 16:56:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.202 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778259382; cv=none; b=nZEZbTY/+xyG3vdA83D/igUab6SzFJPN2NsxsqLVEmCkwdQRZpwF3ZLLFCLzjXUR8qlDo9S03XTJJgoZRAhnjXtDyPsK4KY4RBFAwoJeH3jahxjnpoVS4TF+8fS0/ZCVjzViKcMsmaMSULadmPlwYcL8UeHewBp11fvfRdj92+E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778259382; c=relaxed/simple; bh=66xQ9hvgPBkJ3px3dbJV8/A2nMv9gis7LD/9zeIwN0s=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=fbzJwGzf6r06lzV2wbQzzEdqwlTr5wzBo2BFzbT+6JAhluXcs6//48rpbAR4KIpvDmLzvhSchwhPaYHsNqVRi+0qKzbJMquogqg0fr9hK4qSDH+EedFSACgiZS6PTCWcMA4DKLV3AzYHlM/KYMwoNf+Z9Y4SGXjZQgZTi+gPfGw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=oyl7ZXXQ; arc=none smtp.client-ip=209.85.210.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="oyl7ZXXQ" Received: by mail-pf1-f202.google.com with SMTP id d2e1a72fcca58-82fd55bf6cdso1589319b3a.3 for ; Fri, 08 May 2026 09:56:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1778259380; x=1778864180; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=kPUg8AJeQU9327pVVJCUJnpHdi/ApUr9lgKthU63V1E=; b=oyl7ZXXQxL7cEC/BHpm6kX0yZ6euVkkg/BIku6ZGQT6by9Wk7sUr11IlZVIiR8OaKt r04KgF4IXP5XDaCt2EvW6mrqE9rZFodSKNe3b5R95pdGyvxS5QHFCHhlVYcFsmaJ0oZy F60KhymSnc5KGI7Aj1Mx+4WOJ7o0v+A5XqpDQURgN47ehh7J/w26gSzBet5YSp9gIZUH QUna5H2AeE4eCSrBPngjOWCxF8knooqMGVXfw58VFd9pa5mTNaTXzAHX6SgGxwC+MCGW dnmwaIs21pqdJGrnXgjx0sL7tyGd69pKKzNaUGwX+UAOtXj7k0Q+8+GJZP4euO/PBE9g W3Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778259380; x=1778864180; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=kPUg8AJeQU9327pVVJCUJnpHdi/ApUr9lgKthU63V1E=; b=GlK4y4XgsHpXQlxf5lr7wQzZBBnIh2AZJmj0H/vNRTc/XQnhGAcqWqR8nsZ44EEQOF 6uCRkqkDF7y5TPTGcYMrRxiPPuiSxPR3czWe3TWQTBN32YuVx9k2Ql4QTylEzH2DEx24 w/osHbUC387p3X96S38GrPdH9rA1zy8nMnFwYRGyxPnqf34d3xTiRufpg2z4IaoL5GgP IZGkVgsUuOSnGoirxunV3JuZ+VxJRGh2Kq8psdQii2w+6Sqg25wfWSVu5Hcy0Cm+wXsF LWXo5/aAbgH0gzoKLYStF3VBrBQs1d58hP6VoSLBps426TrSG1CsQUAQ6xCswiy+Qpzg fqJg== X-Forwarded-Encrypted: i=1; AFNElJ9meVQ8Ov5ByhIub5kJwH2vqPP8GEfZd/Krt1Pf4nBOG5QPR4ru0DJcosmZ54S51O3CDUtA8ZUoXQ0PMkM=@vger.kernel.org X-Gm-Message-State: AOJu0YwRIi45g9PQYKKXgtqtdDaOmD+dFGlxluc48Sv+NP24JNr4Txxz heZxA/Nfo78IvW018Gg37dvPU/Y8EdX5c85rFJ5uNndDhyJVY/gSg3BLBbrw+ihG5Xl2j7vID00 qC/rQhg== X-Received: from pfwy14.prod.google.com ([2002:a05:6a00:1c8e:b0:82f:6658:1e84]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:4d98:b0:83d:632e:a8df with SMTP id d2e1a72fcca58-83d632eac6fmr1943881b3a.40.1778259379933; Fri, 08 May 2026 09:56:19 -0700 (PDT) Date: Fri, 8 May 2026 09:56:19 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260506184746.2719880-1-seanjc@google.com> <20260506184746.2719880-3-seanjc@google.com> Message-ID: Subject: Re: [PATCH v2 2/5] KVM: SVM: Always intercept RDMSR for TMCCT (current APIC timer count) From: Sean Christopherson To: Naveen N Rao Cc: Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" On Fri, May 08, 2026, Naveen N Rao wrote: > On Thu, May 07, 2026 at 11:26:15AM -0700, Sean Christopherson wrote: > > The only reg that's at all hot is Timer Initial Count Register, and (a) it's a > > moot point with TSC Deadline mode, and (b) the cost to program hrtimers is so high > > than shaving ~10 cycles is completely meaningless. > > Thanks for the checking this - this was something I wanted to check. And > I agree with your assessment. None of those registers look to be > commonly written to, and ~10 cycles is almost in the noise. If we ever > come across a performance issue, it should be fairly simple to pass > additional registers through (with good reason, of course). > > On a side note, how did you measure this? My naive attempt showed a lot > of variation between runs. I hacked the x86/vmexit.c test in KUT, and then ran it with and without x2APIC: ./x86/run x86/vmexit.flat -smp 2 -cpu qemu64,+x2apic -append apic_wr_lvt0 ./x86/run x86/vmexit.flat -smp 2 -cpu qemu64,-x2apic -append apic_wr_lvt0 That test super useful for micro-benchmarking single instructions and/or short sequences. Even without pinning vCPUs, it does a decent job of generating stable results. diff --git a/x86/vmexit.c b/x86/vmexit.c index 5296ed38..1749cbd8 100644 --- a/x86/vmexit.c +++ b/x86/vmexit.c @@ -22,6 +22,7 @@ struct test { static int nr_cpus; static u64 cr4_shadow; +static u32 lvt0; static void cpuid_test(void) { @@ -447,6 +448,11 @@ static void tscdeadline(void) while (x == 0) barrier(); } +static void apic_wr_lvt0(void) +{ + apic_write(APIC_LVT0, lvt0); +} + static void wr_tsx_ctrl_msr(void) { wrmsr(MSR_IA32_TSX_CTRL, 0); @@ -501,6 +507,7 @@ static struct test tests[] = { { mov_from_cr8, "mov_from_cr8", .parallel = 1, }, { mov_to_cr8, "mov_to_cr8" , .parallel = 1, }, #endif + { apic_wr_lvt0, "apic_wr_lvt0", .parallel = 1, }, { inl_pmtimer, "inl_from_pmtimer", .parallel = 1, }, { inl_nop_qemu, "inl_from_qemu", .parallel = 1 }, { inl_nop_kernel, "inl_from_kernel", .parallel = 1 }, @@ -618,6 +625,7 @@ int main(int ac, char **av) setup_vm(); cr4_shadow = read_cr4(); + lvt0 = apic_read(APIC_LVT0); handle_irq(IPI_TEST_VECTOR, self_ipi_isr); nr_cpus = cpu_count();