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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
To: "Heiko Stübner" <heiko@sntech.de>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Algea Cao" <algea.cao@rock-chips.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>
Cc: kernel@collabora.com, linux-phy@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH 4/4] phy: phy-rockchip-samsung-hdptx: Add clock provider support
Date: Tue, 18 Jun 2024 14:25:16 +0300	[thread overview]
Message-ID: <af51905f-f249-4f4e-8aae-82ff5b585c87@collabora.com> (raw)
In-Reply-To: <2910644.FA0FI3ke8A@diego>

On 6/18/24 10:55 AM, Heiko Stübner wrote:
> Am Montag, 17. Juni 2024, 23:48:12 CEST schrieb Cristian Ciocaltea:
>> The HDMI PHY PLL can be used as an alternative dclk source to RK3588 SoC
>> CRU. It provides more accurate clock rates required by VOP2 to improve
>> existing support for display modes handling, which is known to be
>> problematic when dealing with non-integer refresh rates, among others.
>>
>> It is worth noting this only works for HDMI 2.0 or below, e.g. cannot be
>> used to support HDMI 2.1 4K@120Hz mode.
>>
>> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
>> ---
>>  drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 189 +++++++++++++++++++---
>>  1 file changed, 167 insertions(+), 22 deletions(-)
>>
>> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
>> index 72de287282eb..ad3fd4084377 100644
>> --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
>> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> 
>>  static int rk_hdptx_phy_power_on(struct phy *phy)
>>  {
>>  	struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
>>  	int bus_width = phy_get_bus_width(hdptx->phy);
>> +	int ret;
>> +
>>  	/*
>>  	 * FIXME: Temporary workaround to pass pixel_clk_rate
>>  	 * from the HDMI bridge driver until phy_configure_opts_hdmi
>> @@ -871,20 +925,18 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
>>  	dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
>>  		__func__, bus_width, rate);
>>  
>> -	return rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
>> +	ret = rk_hdptx_phy_consumer_get(hdptx, rate);
>> +	if (!ret)
>> +		ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
> 
> I think this will need a put if _mode_config fails?

Indeed, a forced put variant would be required to ignore any
regmap_read() errors and keep usage_count decremented.  This should be
also used in rk_hdptx_phy_clk_unprepare(), since ->unprepare() callback
cannot fail.

Will get this fixed in v2.

Thanks for reviewing!

Cristian

      reply	other threads:[~2024-06-18 11:25 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-17 21:48 [PATCH 0/4] Add clock provider support to Rockchip RK3588 HDMI TX PHY Cristian Ciocaltea
2024-06-17 21:48 ` [PATCH 1/4] phy: phy-rockchip-samsung-hdptx: Explicitly include pm_runtime.h Cristian Ciocaltea
2024-06-18  7:47   ` Heiko Stübner
2024-06-17 21:48 ` [PATCH 2/4] phy: phy-rockchip-samsung-hdptx: Enable runtime PM at PHY core level Cristian Ciocaltea
2024-06-18  7:51   ` Heiko Stübner
2024-06-17 21:48 ` [PATCH 3/4] dt-bindings: phy: rockchip,rk3588-hdptx-phy: Add #clock-cells Cristian Ciocaltea
2024-06-18  6:42   ` Krzysztof Kozlowski
2024-06-17 21:48 ` [PATCH 4/4] phy: phy-rockchip-samsung-hdptx: Add clock provider support Cristian Ciocaltea
2024-06-18  7:55   ` Heiko Stübner
2024-06-18 11:25     ` Cristian Ciocaltea [this message]

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