From: Mark Brown <broonie@kernel.org>
To: Conor Dooley <conor@kernel.org>
Cc: Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
Cyril Jean <cyril.jean@microchip.com>,
Valentina.FernandezAlanis@microchip.com,
linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH v2 1/3] spi: microchip-core-qspi: control built-in cs manually
Date: Wed, 29 Apr 2026 11:07:29 +0900 [thread overview]
Message-ID: <afFn4dAm3QTzzsAl@sirena.co.uk> (raw)
In-Reply-To: <20260428-perceive-kettle-d42b33eb62bc@spud>
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On Tue, Apr 28, 2026 at 05:12:05PM +0100, Conor Dooley wrote:
> +static void mchp_coreqspi_set_cs(struct spi_device *spi, bool enable)
> +{
> + struct mchp_coreqspi *qspi = spi_controller_get_devdata(spi->controller);
> + u32 val;
> +
> + val = readl(qspi->regs + REG_DIRECT_ACCESS);
> +
> + val &= ~BIT(1);
> + if (spi->mode & SPI_CS_HIGH)
The core already has handling for SPI_CS_HIGH, you shouldn't need to do
it in your driver.
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next prev parent reply other threads:[~2026-04-29 2:07 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-28 16:12 [PATCH v2 0/3] microchip core-qspi gpio-cs fixes + cleanup Conor Dooley
2026-04-28 16:12 ` [PATCH v2 1/3] spi: microchip-core-qspi: control built-in cs manually Conor Dooley
2026-04-29 2:07 ` Mark Brown [this message]
2026-04-28 16:12 ` [PATCH v2 2/3] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations Conor Dooley
2026-04-28 16:12 ` [PATCH v2 3/3] spi: microchip-core-qspi: remove some inline markings Conor Dooley
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