From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6944B3B0ACD for ; Wed, 29 Apr 2026 12:31:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777465875; cv=none; b=GnZMmf2zecvxj9fnS0UD9KDY8Lk6sQAIi+g2thhkW0YS6OdxYhZEqT9D60eZRZvxWNaauOJwUFaPlVQJmNwxJcdklWJEO9ZAKtizMqU9PT2Ti1qKE/yXR7t34oKJL8sXk/J1pwiFEM5T59EPU8O7N7FuAvyVoex5KuQyGLrsATc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777465875; c=relaxed/simple; bh=27iqu5paiKAyhxF/wlVcQQaq58dzy4wowov1IK9WIZU=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=N2wVRr4gEf0EaqnMahTNGAZ1FwDJfH0CD5ATpdASF92W80kAMX+IxeNogo0PRR+g5bLugUsyBg6Az6kMWRZTAj/YaQWDt9n/7XJAHZsAPMqmgjy2WLVOJByo2gbhM2rVXq23oxE9T/h+Uf4OylXtCEDI50IVrzKf0KslcBJkQLA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=HEYzCelb; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="HEYzCelb" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 454682A68 for ; Wed, 29 Apr 2026 05:31:07 -0700 (PDT) Received: from [192.168.0.1] (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 77E133F763 for ; Wed, 29 Apr 2026 05:31:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1777465872; bh=27iqu5paiKAyhxF/wlVcQQaq58dzy4wowov1IK9WIZU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=HEYzCelb7HrHMhkOZVHC0LPorGUPwfWeIg7nWkFm5ZI5zpS4L39aarUmlXgx65vc3 KhThAYJRgx0HxjXqqWWZqQCmm9NO0VJGk/HJbuOfA0Y+J722nyIk+Z9LDewyTjbWW+ bKLSsCBxGcUYUiE15RlIVxjJDIrpxIlgwJ9pGfDE= Date: Wed, 29 Apr 2026 13:31:02 +0100 From: Liviu Dudau To: Boris Brezillon Cc: Steven Price , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 02/10] drm/panthor: Move the register accessors before the IRQ helpers Message-ID: References: <20260429-panthor-signal-from-irq-v1-0-4b92ae4142d2@collabora.com> <20260429-panthor-signal-from-irq-v1-2-4b92ae4142d2@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260429-panthor-signal-from-irq-v1-2-4b92ae4142d2@collabora.com> On Wed, Apr 29, 2026 at 11:38:29AM +0200, Boris Brezillon wrote: > We're about to add an IRQ inline helper using gpu_read(). Move things > around to avoid forward declarations. > > No functional changes. > > Signed-off-by: Boris Brezillon Reviewed-by: Liviu Dudau Best regards, Liviu > --- > drivers/gpu/drm/panthor/panthor_device.h | 142 +++++++++++++++---------------- > 1 file changed, 71 insertions(+), 71 deletions(-) > > diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h > index 3f91ba73829d..768fc1992368 100644 > --- a/drivers/gpu/drm/panthor/panthor_device.h > +++ b/drivers/gpu/drm/panthor/panthor_device.h > @@ -495,6 +495,77 @@ panthor_exception_is_fault(u32 exception_code) > const char *panthor_exception_name(struct panthor_device *ptdev, > u32 exception_code); > > +static inline void gpu_write(void __iomem *iomem, u32 reg, u32 data) > +{ > + writel(data, iomem + reg); > +} > + > +static inline u32 gpu_read(void __iomem *iomem, u32 reg) > +{ > + return readl(iomem + reg); > +} > + > +static inline u32 gpu_read_relaxed(void __iomem *iomem, u32 reg) > +{ > + return readl_relaxed(iomem + reg); > +} > + > +static inline void gpu_write64(void __iomem *iomem, u32 reg, u64 data) > +{ > + gpu_write(iomem, reg, lower_32_bits(data)); > + gpu_write(iomem, reg + 4, upper_32_bits(data)); > +} > + > +static inline u64 gpu_read64(void __iomem *iomem, u32 reg) > +{ > + return (gpu_read(iomem, reg) | ((u64)gpu_read(iomem, reg + 4) << 32)); > +} > + > +static inline u64 gpu_read64_relaxed(void __iomem *iomem, u32 reg) > +{ > + return (gpu_read_relaxed(iomem, reg) | > + ((u64)gpu_read_relaxed(iomem, reg + 4) << 32)); > +} > + > +static inline u64 gpu_read64_counter(void __iomem *iomem, u32 reg) > +{ > + u32 lo, hi1, hi2; > + do { > + hi1 = gpu_read(iomem, reg + 4); > + lo = gpu_read(iomem, reg); > + hi2 = gpu_read(iomem, reg + 4); > + } while (hi1 != hi2); > + return lo | ((u64)hi2 << 32); > +} > + > +#define gpu_read_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us) \ > + read_poll_timeout(gpu_read, val, cond, delay_us, timeout_us, false, \ > + iomem, reg) > + > +#define gpu_read_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ > + timeout_us) \ > + read_poll_timeout_atomic(gpu_read, val, cond, delay_us, timeout_us, \ > + false, iomem, reg) > + > +#define gpu_read64_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us) \ > + read_poll_timeout(gpu_read64, val, cond, delay_us, timeout_us, false, \ > + iomem, reg) > + > +#define gpu_read64_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ > + timeout_us) \ > + read_poll_timeout_atomic(gpu_read64, val, cond, delay_us, timeout_us, \ > + false, iomem, reg) > + > +#define gpu_read_relaxed_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ > + timeout_us) \ > + read_poll_timeout_atomic(gpu_read_relaxed, val, cond, delay_us, \ > + timeout_us, false, iomem, reg) > + > +#define gpu_read64_relaxed_poll_timeout(iomem, reg, val, cond, delay_us, \ > + timeout_us) \ > + read_poll_timeout(gpu_read64_relaxed, val, cond, delay_us, timeout_us, \ > + false, iomem, reg) > + > #define INT_RAWSTAT 0x0 > #define INT_CLEAR 0x4 > #define INT_MASK 0x8 > @@ -629,75 +700,4 @@ static inline void panthor_ ## __name ## _irq_disable_events(struct panthor_irq > > extern struct workqueue_struct *panthor_cleanup_wq; > > -static inline void gpu_write(void __iomem *iomem, u32 reg, u32 data) > -{ > - writel(data, iomem + reg); > -} > - > -static inline u32 gpu_read(void __iomem *iomem, u32 reg) > -{ > - return readl(iomem + reg); > -} > - > -static inline u32 gpu_read_relaxed(void __iomem *iomem, u32 reg) > -{ > - return readl_relaxed(iomem + reg); > -} > - > -static inline void gpu_write64(void __iomem *iomem, u32 reg, u64 data) > -{ > - gpu_write(iomem, reg, lower_32_bits(data)); > - gpu_write(iomem, reg + 4, upper_32_bits(data)); > -} > - > -static inline u64 gpu_read64(void __iomem *iomem, u32 reg) > -{ > - return (gpu_read(iomem, reg) | ((u64)gpu_read(iomem, reg + 4) << 32)); > -} > - > -static inline u64 gpu_read64_relaxed(void __iomem *iomem, u32 reg) > -{ > - return (gpu_read_relaxed(iomem, reg) | > - ((u64)gpu_read_relaxed(iomem, reg + 4) << 32)); > -} > - > -static inline u64 gpu_read64_counter(void __iomem *iomem, u32 reg) > -{ > - u32 lo, hi1, hi2; > - do { > - hi1 = gpu_read(iomem, reg + 4); > - lo = gpu_read(iomem, reg); > - hi2 = gpu_read(iomem, reg + 4); > - } while (hi1 != hi2); > - return lo | ((u64)hi2 << 32); > -} > - > -#define gpu_read_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us) \ > - read_poll_timeout(gpu_read, val, cond, delay_us, timeout_us, false, \ > - iomem, reg) > - > -#define gpu_read_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ > - timeout_us) \ > - read_poll_timeout_atomic(gpu_read, val, cond, delay_us, timeout_us, \ > - false, iomem, reg) > - > -#define gpu_read64_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us) \ > - read_poll_timeout(gpu_read64, val, cond, delay_us, timeout_us, false, \ > - iomem, reg) > - > -#define gpu_read64_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ > - timeout_us) \ > - read_poll_timeout_atomic(gpu_read64, val, cond, delay_us, timeout_us, \ > - false, iomem, reg) > - > -#define gpu_read_relaxed_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ > - timeout_us) \ > - read_poll_timeout_atomic(gpu_read_relaxed, val, cond, delay_us, \ > - timeout_us, false, iomem, reg) > - > -#define gpu_read64_relaxed_poll_timeout(iomem, reg, val, cond, delay_us, \ > - timeout_us) \ > - read_poll_timeout(gpu_read64_relaxed, val, cond, delay_us, timeout_us, \ > - false, iomem, reg) > - > #endif > > -- > 2.53.0 > -- ==================== | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --------------- ¯\_(ツ)_/¯