From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7798535B62C for ; Thu, 30 Apr 2026 18:15:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.202 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777572906; cv=none; b=p9w97E36XHPtdAH+ZW2lDFMwannUXmY5Ot+JfooKR+3QntwIlliYMMCWSXvhY73V2/313JkSlEb64yNk2IiPl+T0VbwNzQIj5TKT/BG9rBXzhjuo2bXM/Ih7V4WS9AYD6WeBz1JabC/SRyXvHXw9Y0k/q4fNJu43vzD0LkCB/Ss= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777572906; c=relaxed/simple; bh=JrorKwYUHH4zZ4zy+pqcEJAl4tqafS2Mqv4yUo/QuME=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=FDU75j2jkhuLBLBvB44GQ/R/VJLyUxJQ/PzXlzLUDpHTuGLnL3q08c1ARgzCKlvtRvAAmOfg4E5Sdpn09NpdnrWzV5o5CeKtcs3ANun3uynnARu2VY8zy4wltylGsUu5nWTHaT/WnfMLIKJFBkEtTVHyNQk/ltKOepPOraBNoqg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=a4vJLKU4; arc=none smtp.client-ip=209.85.214.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="a4vJLKU4" Received: by mail-pl1-f202.google.com with SMTP id d9443c01a7336-2b9a6b13826so19077875ad.1 for ; Thu, 30 Apr 2026 11:15:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1777572905; x=1778177705; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=C1+2Il3IVXV0VYL0NW7a1NeGzgz+qodUBQceYiBkkQc=; b=a4vJLKU4M+tUxBuivkM1puVBf1FjmzvjXKcoGjIALFQrogFC84KMk/r08NzBV8pYSa MLTbiDgvxn9BSXahJA9L097EQAKx/YMROSY2K77epTGUhGJO9rTmldeHIXBwniP7KIa5 T8T3X/tRPAWWEEFboqMETcdsYve5Wi7c0e1BlLt2/7USMc+zvXEh67ZU1zrcdgteLW60 B2mX9SPI5kN+DYHQm3NjzAZkXqOX7VFltXWWpjgikaTkOzRHGd/NdBRLt5dYL0e6xV3Y KD/OAL3WVs4IpDzhhzviYG7tAL4hGV9zJz2KTAqPFbC4MutzyV4e3tVqw3d1b8xsQ57J qdbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777572905; x=1778177705; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=C1+2Il3IVXV0VYL0NW7a1NeGzgz+qodUBQceYiBkkQc=; b=oTHZs4t3Y6qD7YOzE1EUvwB9ZKsVhgb8YoG+yzGzZmnIHMejsvCzHW1A3t2KuTt6Bg nVJBXTBwautZ+56r2j2ZvmOc12MhWhJm5ITncinLShrf7vX4YjC7vrdPoUrqhiYEhbOj GfMG8tv/VTjCi3Fb+6NDQwq6lUu0VyRyFPYQNAnaAimd/sLfSP2NprYCYYDf75JZGZ8X Clvz03xvfX4UywChZJr1eZ81434/KeHRqJkEO7Doz7xe3pkareDpF+xYzhJ8NCozovc5 awATFSfL6RZ28CF47nrl3wUt5tHjmyKfUwNWKGjX22LhCnk5bziwrvgDvfU1flqs89Zn TMlw== X-Gm-Message-State: AOJu0Yzoc+tzuPXqlHVk4z3DYeE6aLTywczoq/B1Goq0QXDmRTSjERJE sRA2C9QqvJ7t3RH/1geyibxo2ZFR1oEhq8BzSS92k0oLGNvwLC06wJA7hElDT/1PbMaU5gofmHJ jG7xANw== X-Received: from plpa5.prod.google.com ([2002:a17:902:9005:b0:2b2:a488:ae47]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:2ed0:b0:2b2:4a9a:b168 with SMTP id d9443c01a7336-2b9a23175c0mr42550985ad.11.1777572904545; Thu, 30 Apr 2026 11:15:04 -0700 (PDT) Date: Thu, 30 Apr 2026 11:15:03 -0700 In-Reply-To: <20260430150747.76749-5-pbonzini@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260430150747.76749-1-pbonzini@redhat.com> <20260430150747.76749-5-pbonzini@redhat.com> Message-ID: Subject: Re: [PATCH 04/28] KVM: x86/mmu: shuffle high bits of SPTEs in preparation for MBEC From: Sean Christopherson To: Paolo Bonzini Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, d.riley@proxmox.com, jon@nutanix.com Content-Type: text/plain; charset="us-ascii" On Thu, Apr 30, 2026, Paolo Bonzini wrote: > Access tracking will need to save bit 10 when MBEC is enabled. > Right now it is simply shifting the R and X bits into bits 54 and 56, > but bit 10 would not fit with the same scheme. Reorganize the > high bits so that access tracking will use bits 52, 54 and 62. > As a side effect, the free bits are compacted slightly, with > 56-59 still unused. > @@ -84,8 +94,8 @@ static_assert(!(SPTE_TDP_AD_MASK & SHADOW_ACC_TRACK_SAVED_MASK)); > * to not overlap the A/D type mask or the saved access bits of access-tracked > * SPTEs when A/D bits are disabled. > */ > -#define EPT_SPTE_HOST_WRITABLE BIT_ULL(57) > -#define EPT_SPTE_MMU_WRITABLE BIT_ULL(58) FWIW, I originally chose bits 57 and 58 so that HOST-writable and MMU-writable would occupy the high byte, e.g. for faster access (in theory). But that's uninteresting in practice because the mask is stored in a global variable, i.e. the compiler can't optimize the SPTE access anyways.