From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 843311AA1F4 for ; Fri, 1 May 2026 14:16:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777644991; cv=none; b=dv9aHimExcqselgZARJpS6G1n3PST376RbDxCMCC1qLNOOTpZ2AZq6pI+Nx0qTzoZDCIgK1FQaF5Usk+nQ9N9evXQJAIdSiG4HELmcR/Fc+V/yWXDabf+ECFjsIESAyKnSzgT3FEaxs2diPDULkRL3B+g75F1VitjikVaeQNKig= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777644991; c=relaxed/simple; bh=BayNa5jbz0M4jvagJ0bgGlBgBI0tYgCb5eIEkJ2Mmqw=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=EQ99K3rHIhr8q0G5NNw+gZoege4Usg8wrj9uV4x210gqUmuRyoGxM8WrZeEnW13D8ZbSpPBxCkflxxamAXvxCr+EUXh6z2xYKe6UDB5Jok5TxSbEXUTAwZk7KjEJgZWYI6TRW72BFBJpR1bRpDr7S1CmGnN4dpNeOlbGuC9FY9k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=hxNIlQxl; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="hxNIlQxl" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 706632A9A; Fri, 1 May 2026 07:16:23 -0700 (PDT) Received: from arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E57AB3F7B4; Fri, 1 May 2026 07:16:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1777644988; bh=BayNa5jbz0M4jvagJ0bgGlBgBI0tYgCb5eIEkJ2Mmqw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=hxNIlQxl/Cc35oPga4quxc30zuSS+wR7D1y58Bxd69AqzHhrwDi+YoOyF1lX/bHz+ fghYsV3F27IHNwoExqu4JjbMY/pr+tB4GKLCnI66w5ySpHxtC2yAlYeZhuzM9KDcwj 4vQqc1LIRvEKHMzcSaIwIWlcBA+/+ITuSIUbZbGA= Date: Fri, 1 May 2026 15:16:20 +0100 From: Catalin Marinas To: "zhangpengjie (A)" Cc: will@kernel.org, maz@kernel.org, timothy.hayes@arm.com, lpieralisi@kernel.org, mrigendra.chaubey@gmail.com, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, zhanjie9@hisilicon.com, zhenglifeng1@huawei.com, lihuisong@huawei.com, yubowen8@huawei.com, linhongye@h-partners.com, linuxarm@huawei.com, wangzhi12@huawei.com Subject: Re: [PATCH v2] arm64: smp: Do not mark secondary CPUs possible under nosmp Message-ID: References: <20260423134654.4178271-1-zhangpengjie2@huawei.com> <49f96032-6027-4c79-8d08-9545261e553f@huawei.com> <1b1b1319-2f98-4b5d-85ec-6fc4150b6f85@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1b1b1319-2f98-4b5d-85ec-6fc4150b6f85@huawei.com> On Thu, Apr 30, 2026 at 05:54:35PM +0800, zhangpengjie (A) wrote: > On 4/30/2026 5:34 PM, zhangpengjie (A) wrote: > > On 4/27/2026 9:20 PM, Catalin Marinas wrote: > > > On Thu, Apr 23, 2026 at 09:46:54PM +0800, Pengjie Zhang wrote: > > > > Under nosmp (maxcpus=0), arm64 never brings up secondary CPUs. > > > > > > > > However, arm64 still enumerates firmware-described CPUs during SMP > > > > initialization, which can leave secondary CPUs visible to > > > > for_each_possible_cpu() users even though they never reach the > > > > bringup path in this configuration. > > > > > > > > This is not just a cosmetic mask mismatch: code iterating over > > > > possible CPUs may observe secondary CPU per-CPU state that is never > > > > fully initialized under nosmp. > > > I'm fine with the patch in principle but I fail to see why it is not > > > mostly cosmetic. If we have possible & !present CPUs (there's another > > > thread around cpuhp_smt_enable() to allow this combination on arm64), > > > get_cpu_device() would return NULL and the core code is supposed to > > > handle this. What other per-CPU state should be initialised for a > > > possible CPU but it is not without this patch? [...] > Yes, possible-but-not-present CPUs are valid in the general hotplug > model. The nosmp/maxcpus=0 case is different though: on arm64, > smp_prepare_cpus() treats this as a UP-mandated boot and returns before > marking secondary CPUs present, so these CPUs are deliberately kept out of > the bringup path for this boot. > > The kind of issue I had in mind was subsystem-owned per-CPU state where > iteration follows cpu_possible_mask but the state is populated only from > CPU online/probe paths. The CPPC nosmp issue fixed by commit 15eece6c5b05 > ("ACPI: CPPC: Fix NULL pointer dereference when nosmp is used") was the > kind of mismatch I was thinking of, although CPPC itself has already been > fixed to use online CPUs where appropriate. > > I agree the changelog overstates this. I can respin with a toned-down > changelog if you prefer. Please do. Since it's not an urgent fix, I'll leave it for 7.2. With the commit text changed: Reviewed-by: Catalin Marinas