Re: [PATCH v3 6/7] PCI: xilinx-nwl: Add phy support

Markus Elfring
2024-05-24T15:36:36Z

>> …
>>> +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
>> …
>>> @@ -818,12 +876,15 @@ static int nwl_pcie_probe(struct platform_device *pdev)
>>> err = nwl_pcie_enable_msi(pcie);
>>> if (err < 0) {
>>> dev_err(dev, "failed to enable MSI support: %d\n", err);
>>> - goto err_clk;
>>> + goto err_phy;
>>> }
>>> }
>>>
>>> err = pci_host_probe(bridge);
>>>
>>> +err_phy:
>>> + if (err)
>>> + nwl_pcie_phy_disable(pcie);
>>> err_clk:
>>> if (err)
>>> clk_disable_unprepare(pcie->clk);
>>
>> I got the impression that some source code adjustments should be performed
>> in another separate update step for this function implementation.
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.9#n81
>>
>> You propose to extend the exception handling here.
>> Does such information indicate a need for another tag “Fixes”?
>
> Huh? I am only disabling what I enabled...

* Was a resource deactivation accidentally missing in a previous release
of this software component?

* Can repeated checks be avoided a bit more by a design approach which we tried
to clarify for the update step “[PATCH v3 5/7] PCI: xilinx-nwl: Clean up clock
on probe failure/removal”?
https://lore.kernel.org/lkml/bb9e239f-902b-4f52-a5e9-98c29b360418@linux.dev/

Regards,
Markus