From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E1D1C43603 for ; Tue, 10 Dec 2019 11:49:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EDF702073B for ; Tue, 10 Dec 2019 11:49:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727544AbfLJLtc (ORCPT ); Tue, 10 Dec 2019 06:49:32 -0500 Received: from mga11.intel.com ([192.55.52.93]:4591 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727223AbfLJLtc (ORCPT ); Tue, 10 Dec 2019 06:49:32 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Dec 2019 03:49:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,299,1571727600"; d="scan'208";a="295868192" Received: from linux.intel.com ([10.54.29.200]) by orsmga001.jf.intel.com with ESMTP; 10 Dec 2019 03:49:31 -0800 Received: from [10.125.252.242] (abudanko-mobl.ccr.corp.intel.com [10.125.252.242]) by linux.intel.com (Postfix) with ESMTP id 01EEA580A3B; Tue, 10 Dec 2019 03:49:29 -0800 (PST) Subject: Re: [PATCH] perf/x86/intel: Fix PT PMI handling To: Alexander Shishkin , Peter Zijlstra Cc: Arnaldo Carvalho de Melo , Ingo Molnar , linux-kernel@vger.kernel.org, Jiri Olsa , Vitaly Slobodskoy , stable@vger.kernel.org References: <20191210105101.77210-1-alexander.shishkin@linux.intel.com> From: Alexey Budankov Organization: Intel Corp. Message-ID: Date: Tue, 10 Dec 2019 14:49:28 +0300 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: <20191210105101.77210-1-alexander.shishkin@linux.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10.12.2019 13:51, Alexander Shishkin wrote: > Commit: > > ccbebba4c6bf ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it") > > skips the PT/LBR exclusivity check on CPUs where PT and LBRs coexist, but > also inadvertently skips the active_events bump for PT in that case, which > is a bug. If there aren't any hardware events at the same time as PT, the > PMI handler will ignore PT PMIs, as active_events reads zero in that case, > resulting in the "Uhhuh" spurious NMI warning and PT data loss. > > Fix this by always increasing active_events for PT events. > > Signed-off-by: Alexander Shishkin > Fixes: ccbebba4c6bf ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it") > Reported-by: Vitaly Slobodskoy > Cc: stable@vger.kernel.org # v4.7 > --- > arch/x86/events/core.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) Acked-by: Alexey Budankov > > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > index 6e3f0c18908e..5a736197dfa4 100644 > --- a/arch/x86/events/core.c > +++ b/arch/x86/events/core.c > @@ -375,7 +375,7 @@ int x86_add_exclusive(unsigned int what) > * LBR and BTS are still mutually exclusive. > */ > if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) > - return 0; > + goto out; > > if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { > mutex_lock(&pmc_reserve_mutex); > @@ -387,6 +387,7 @@ int x86_add_exclusive(unsigned int what) > mutex_unlock(&pmc_reserve_mutex); > } > > +out: > atomic_inc(&active_events); > return 0; > > @@ -397,11 +398,15 @@ int x86_add_exclusive(unsigned int what) > > void x86_del_exclusive(unsigned int what) > { > + atomic_dec(&active_events); > + > + /* > + * See the comment in x86_add_exclusive(). > + */ > if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) > return; > > atomic_dec(&x86_pmu.lbr_exclusive[what]); > - atomic_dec(&active_events); > } > > int x86_setup_perfctr(struct perf_event *event) >