From: Inochi Amaoto <inochiama@gmail.com>
To: Krzysztof Kozlowski <krzk@kernel.org>,
Inochi Amaoto <inochiama@gmail.com>
Cc: Vinod Koul <vkoul@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Yixun Lan <dlan@kernel.org>,
Kees Cook <kees@kernel.org>,
"Gustavo A. R. Silva" <gustavoars@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Ze Huang <huang.ze@linux.dev>,
Alex Elder <elder@riscstar.com>,
linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org,
Yixun Lan <dlan@gentoo.org>, Longbin Li <looong.bin@gmail.com>
Subject: Re: [PATCH 1/2] dt-bindings: phy: Add Spacemit K3 USB3/PCIe comb phy support
Date: Mon, 4 May 2026 18:20:59 +0800 [thread overview]
Message-ID: <afhx6C2EvDbMJc92@inochi.infowork> (raw)
In-Reply-To: <20260504-logical-nice-python-1e1f43@quoll>
On Mon, May 04, 2026 at 11:54:11AM +0200, Krzysztof Kozlowski wrote:
> On Thu, Apr 30, 2026 at 10:28:40AM +0800, Inochi Amaoto wrote:
> > +properties:
> > + compatible:
> > + const: spacemit,k3-comb-phy
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + "#phy-cells":
> > + const: 2
> > + description:
> > + The first one is phy id, the second one is phy type.
>
> You could mention here the defines representing supported phy types.
>
OK.
> > +
> > + spacemit,apb-spare:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + Phandle to APB SPARE system controller interface, used for
> > + PHY calibration.
> > +
> > + spacemit,apmu:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + items:
> > + - items:
> > + - description: phandle of APMU syscon
> > + - description: configuration of the PHY lanes
> > + description: |
> > + Phandle to control PHY mux configuration. The configuration
> > + is described as follows:
> > + bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode
> > + bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode
> > + bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode
> > + bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode
> > + bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode
>
> I assume this device k3-comb-phy handles phys for PCIe A, B, C and D?
>
In fact it handles phys for PCIe A-E. The mux for the phy of PCIe E
(the id is 5) is controlled by bit 4. If the comb PHY is in shared
mode, the PCIe E always got one lane.
I think it is good to add a public link for this configuration, but
Spacemit has no opened any document for this publicly....
> > +
> > + The bit[3:0] is only valid when bit 4 is 1.
> > +
> > +required:
> > + - compatible
>
> reg required.
>
It is fine for me
> > + - "#phy-cells"
> > + - spacemit,apb-spare
> > + - spacemit,apmu
> > +
> > +additionalProperties: false
>
> Best regards,
> Krzysztof
>
Regards,
Inochi
next prev parent reply other threads:[~2026-05-04 10:21 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-30 2:28 [PATCH 0/2] riscv: spacemit: Add K3 PCIe/USB comb phy support Inochi Amaoto
2026-04-30 2:28 ` [PATCH 1/2] dt-bindings: phy: Add Spacemit K3 USB3/PCIe " Inochi Amaoto
2026-05-04 9:54 ` Krzysztof Kozlowski
2026-05-04 10:20 ` Inochi Amaoto [this message]
2026-04-30 2:28 ` [PATCH 2/2] phy: spacemit: Add USB3/PCIe comb PHY driver for Spacemit K3 Inochi Amaoto
2026-04-30 7:39 ` Ze Huang
2026-05-01 4:05 ` Inochi Amaoto
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