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Peter Anvin" , Shuah Khan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, "Saenz Julienne, Nicolas" , Maciej Wieczor-Retman , Tom Lendacky , Shivansh Dhiman , Neeraj Upadhyay Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable +AMD folks On Thu, May 07, 2026, Sean Christopherson wrote: > On Thu, May 07, 2026, Andrew Cooper wrote: > > On 07/05/2026 3:08 pm, Sean Christopherson wrote: > > > On Thu, May 07, 2026, David Woodhouse wrote: > > >> From: David Woodhouse > > >> > > >> ICEBP (INT1, opcode 0xF1) generates a #DB that is architecturally a > > >> trap, but on SVM it was not always intercepted. Unconditionally > > >> intercept ICEBP on SVM to match VMX behaviour and ensure correct > > >> event delivery semantics. > > >> > > >> Add two selftests exercising ICEBP: > > >> > > >> - int1_ept_test: verifies that ICEBP works correctly when the > > >> exception stack page is not present (EPT/NPT fault during #DB > > >> delivery). The IST stack is evicted via MADV_DONTNEED before > > >> executing INT1. > > >> > > >> - int1_task_gate_test: verifies ICEBP delivery through a 32-bit > > >> task gate, exercising the legacy task-switch path for #DB. > > >> > > >> Tested on Intel Sapphire Rapids and AMD Genoa. Without the SVM fix, > > >> int1_task_gate_test fails on AMD with EIP pointing at ICEBP instead > > >> of after it. With the fix, both tests pass on both platforms. > > > Hmm, but KVM unconditionally intercepts task switches. Is this effec= tively working > > > around a bug in task_switch_interception()? > >=20 > > Not really.=C2=A0 It's a bug/misfeature in AMD CPUs. > >=20 > > When you get TASK_SWITCH (which always has fault semantics), you look a= t > > the vectoring event type to decide whether it was logically caused by a > > trap, and therefore whether to move %rip forwards before entering the > > new task. > >=20 > > AMD CPUs don't distinguish instruction-induced #DBs (i.e. ICEBP) from > > exception-induced #DBs (all others), and also don't report an > > instruction length for an ICEBP-induced TASK_SWITCH. >=20 > Heh, that explains why I couldn't find an equivalent of INTR_TYPE_PRIV_SW= _EXCEPTION > in the SVM code. Dragging in a comment/concern Andrew raised offlist. If AMD doesn't provid= e or *allow* the equivalent of INTR_TYPE_PRIV_SW_EXCEPTION, i.e. type 5, then wh= at happens when KVM needs to inject an INT1 #DB with FRED enabled? Per Intel'= s FRED spec, which presumably AMD is following, the event type is shoved onto the = stack: =E2=80=94 For INT1, the event stack level is IA32_FRED_STKLVLS[3:2]. Th= e event type is 5 (privileged software exception) and the vector is 1. But if SVM doesn't support SVM_EVTINJ_TYPE_INT1, then realistically this ca= n't work (no way in hell is KVM going to emulate FRED event delivery). Does FR= ED on AMD even do the right thing for INT1 without SVM? > > The workaround is to intercept ICEBP unconditionally, handle the > > FAULT->TRAP conversion in the hypervisor, at which point the #DB-induce= d > > TASK_SWITCH occurs with %rip on the correct instruction boundary whethe= r > > it was instruction-induced or exception-induced. > >=20 > > ~Andrew