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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2f56f7967cfsm9504959eec.19.2026.05.07.10.46.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2026 10:46:36 -0700 (PDT) Date: Thu, 7 May 2026 10:46:34 -0700 From: Jack Pham To: Konrad Dybcio , Thinh Nguyen Cc: Konrad Dybcio , Greg Kroah-Hartman , Mathias Nyman , "linux-usb@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "usb4-upstream@oss.qualcomm.com" , Raghavendra Thoorpu , Mika Westerberg Subject: Re: [PATCH 2/2] usb: dwc3: Notify XHCI core of tunneled status Message-ID: References: <20260505-topic-dwc3_tunneling_state-v1-0-4aaa6c3c14cb@oss.qualcomm.com> <20260505-topic-dwc3_tunneling_state-v1-2-4aaa6c3c14cb@oss.qualcomm.com> <1163a026-03b2-4860-a422-eb276920b4aa@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1163a026-03b2-4860-a422-eb276920b4aa@oss.qualcomm.com> X-Authority-Analysis: v=2.4 cv=TJB1jVla c=1 sm=1 tr=0 ts=69fccffe cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=DJ0P9IFMZVm84kehXPgA:9 a=CjuIK1q_8ugA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA3MDE3OSBTYWx0ZWRfXyvkkM34zpePb sPvp28GqGRVUiw1TunQc5Oa5QpC2wuIsvXSUD5Z7bYA/VdszyZLvQs0RQcA0eUrydd6kiVjAZ4g hbxdaZyknWPKgTvvUfwdNGkPL11OpnyNObtxfWrqJ3NShXiKLn3QH3sB59D5ymgqA1jOyQj5QB3 HjTYzICdyozlf/vxyxR1/6bKXWipiIwpHVE/nIbTYwMpBhsPD739RqvFXYp19U1hHpwjQysozpg t9fWLy8m7g1ZhAcvcBRW8kI2Qvdsi07Yi+cOXIyDYvkc+Mz1ikGCqz2aG+LiT//4ZsUWjK08cPc ETnnSu2Jh8y3krecJQqIHhSt00MscjX5DxpwjNEYS+99T6MXCYjn8453yFUbUMnDfRoGMEl+mNi y4o8kt9r13mNyGwA+YYrZu3DsLGmSvgpdp87rgWUuAM/gCAfNKdXsv0QsBBl12Dadrt18ZUgwCU eY2kZvgoz6v0ojH1qnw== X-Proofpoint-GUID: mMoKV_LDTatA82WX0CXBErHi8ZNawmcg X-Proofpoint-ORIG-GUID: mMoKV_LDTatA82WX0CXBErHi8ZNawmcg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-07_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 priorityscore=1501 adultscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605070179 On Thu, May 07, 2026 at 12:34:50PM +0200, Konrad Dybcio wrote: > On 5/7/26 1:40 AM, Thinh Nguyen wrote: > > On Tue, May 05, 2026, Konrad Dybcio wrote: > >> From: Konrad Dybcio > >> > >> The Thunderbolt framework relies on the USB core to create device links > >> for tunneled ports, so that the USB3 controller is only kept > >> runtime-resumed for the duration of the tunneling. This depends on > >> first knowing whether a connection is tunneled or native. > >> > >> Add the logic to handle that for DWC3 controllers. > >> > >> Signed-off-by: Konrad Dybcio > >> --- > >> drivers/usb/dwc3/core.c | 12 ++++++++++++ > >> drivers/usb/dwc3/core.h | 18 ++++++++++++++++++ > >> drivers/usb/dwc3/host.c | 12 ++++++++++++ > >> 3 files changed, 42 insertions(+) > >> > >> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c > >> index 65213896de99..7cec4911e278 100644 > >> --- a/drivers/usb/dwc3/core.c > >> +++ b/drivers/usb/dwc3/core.c > >> @@ -162,6 +162,18 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy) > >> } > >> EXPORT_SYMBOL_GPL(dwc3_set_prtcap); > >> > >> +enum usb_link_tunnel_mode dwc3_link_tunnel_mode(struct dwc3 *dwc, u8 port) > >> +{ > >> + /* Prior versions had no CIO support */ > >> + if (!DWC3_VER_IS_WITHIN(DWC31, 191A, ANY)) > >> + return USB_LINK_NATIVE; > >> + > >> + if (dwc3_readl(dwc, DWC3_CIOCTRL(port)) & DWC3_CIOCTRL_CIO_EN) > > > > The CIO register block only exists if DWC1_USB31_EN_CIO is set (and > > DWC_USB31_EN_USB2_ONLY is not set). In most cases, this register block > > will be reserved, register read of reserved block should be 0. But we > > can't guarantee that it will always be the case. > > That's inconvenient because.. > > [...] > > > We shouldn't need to be doing this. This should be checked from the > > xHCI driver. Check xHCI spec for PORTSC.TM and USB3 tunneling support > > capability (section 7.11). > > ..I'm seeing only caps 0/1/2 (and 10 on some but not all) advertised > (I ran a for-loop checking offsets 0..=255) Right. That section in xHCI spec was only added in the 1.2b revision. However the DWC31 IP versions that current Qualcomm USB4-capable SoCs are using are 2.00a (and a customized version of 1.91a) which are only compliant to xHCI 1.1 so this capability is not there, even though the CIO register block exists. So short of having the proper XHCI bit, this is the next best, non-SoC specific alternative we've found that can allow XHCI driver to identify when it is operating in tunnel mode. Jack