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Tue, 19 May 2026 23:38:37 -0700 Date: Tue, 19 May 2026 23:38:35 -0700 From: Nicolin Chen To: "Tian, Kevin" CC: Will Deacon , Robin Murphy , "Joerg Roedel" , Bjorn Helgaas , "Jason Gunthorpe" , "Rafael J . Wysocki" , "Len Brown" , Pranjal Shrivastava , "Mostafa Saleh" , Lu Baolu , "linux-arm-kernel@lists.infradead.org" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , "linux-pci@vger.kernel.org" , Vikram Sethi , Shuai Xue Subject: Re: [PATCH v4 00/24] iommu/arm-smmu-v3: Quarantine device upon ATC invalidation timeout Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B36D:EE_|DM6PR12MB4092:EE_ X-MS-Office365-Filtering-Correlation-Id: f636b2f9-1e0a-43dd-7471-08deb63a790f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700016|1800799024|30052699003|82310400026|22082099003|18002099003|56012099003|13003099007|11063799006|4143699003; X-Microsoft-Antispam-Message-Info: HX7l02A34/zG+Ecv+RDvSKB0k2++6jkwEAThbmcd8yY4HgApiDNLkk+5KWZRJWpKlOM023P0ysaIK4WW/qYrBrzj2fDUXoWEPr+dlzcWJUJtusdxglX/C+Tei14S8qlDfVBZgpTNW8EQVOGejYFCLKZdedqqTIYVhY0HJui3UmucdLq4l1CCB9epmqRnP0IJSwIkWlRkEVF4s4VNyE1+44Hr9LkxjIGO0ZWk6KEMGC0lfV70yH8x78lVl8XSFfTwOsH1QqB9ziTFkeBsRM2pZOVUEv79eg7BV9mVUYHiuR4joRrgw0OUo7HfL05oP1kCW3J3wko/c4/OlmBYSkwQy4a/vTPCKxJ3hI1XJKtMoMx+LfgFx1G4flbpEvgKNm22Z7UdcWGfvaSBMFH3bsR4sdtmFbOKC/TECKDNjwqg9MhZxvffh+lsp4tYOeapHXsQu0+YEZhu4rfeGkVR7D6MzxrWYmu4+8ub3kCCKPiqs6W+TXK7/VfOAVTmi7kYqDVRpgEoHaMV0VI+UTPG89qNUIM7/Ru5U/dxx2iX43+sxJa2f3/tJdvuCXUxxMxOtbavYQEQUfMl+SoRHd66M2fkuuIGwQh792Cygq3tWRTKPgLOLbXbRJXmFwnFqax1x2NOA626xhu848VrZNH/rQ2KfJL9OVkHaGkctR35TVbMsGSy2RVPua+ppVHntRTGrHgoO9U83W88fgSlpUKaEBP0b8QlFqDxtmvshVify5XelkG3R/1ouIcB9qABoMDNCcFG X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700016)(1800799024)(30052699003)(82310400026)(22082099003)(18002099003)(56012099003)(13003099007)(11063799006)(4143699003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ZJmd1JsB9PhYnTsvNa+ALOe9taQSZq075qsodcivGwY9FqackR/KibDQ+OaSvCHwbjTGs92oqW/IhliAzBkE4SGORf8t854hNGTzTT5p9ukP47Xcq9TAN/51we4ycJg5FJa29CD4HPqA2R4PbMJKogMfDzNDQXZAEFSzpg1WxZhMT+YA8pQ+cGqf8rwN9xwBWoKWEFfQAuZIcZJCVlprnaVbx8yxnx+MArtpzxrJxsKfhZjzCorzevP595CgvBQFnvjzxqlXr7+6S3CGv/qcR4u1rFLq7Sen2qD3KQD77QyMxt1nw68wRjiGzBBLV0Fo3FiYimKt5R8ejv3hO08cEge4e4Th7nmRecD40/ERs9I1s6LYUUviRyYHFySD9Ge9EoY4BQQzf2fc3ABx3Yc4APpqBxngXOJ+F6RRJ7VeDwNzC/B97rBAcr4tTSe1qF7d X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2026 06:38:58.6701 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f636b2f9-1e0a-43dd-7471-08deb63a790f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B36D.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4092 On Wed, May 20, 2026 at 03:59:43AM +0000, Tian, Kevin wrote: > > From: Nicolin Chen > > Sent: Tuesday, May 19, 2026 11:39 AM > > > > Changelog > > v4: > > * Rebase on Joerg's IOMMU "fixes" branch > > * Rebase on Jason's SMMUv3 cmd_ent series > > https://lore.kernel.org/all/0-v2-47b2bf710ad5+716ac- > > smmu_no_cmdq_ent_jgg@nvidia.com/ > > * [PCI] Don't suspend IOMMU in probe mode > > * [iommu] kfree_rcu() iommu_group > > * [iommu] Convert gdev->blocked to enum gdev_blocked > > * [iommu] Use disable_work_sync() to fix UAF and ref leak > > * [iommu] Gate done() transitions to preserve BLOCKED_BROKEN > > * [iommu] Decrement recovery_cnt when unplugging a blocked gdev > > * [iommu] Drop racy dev_has_iommu() in iommu_report_device_broken() > > * [iommu] Add gdev->broken_pending to skip worker after racing recovery > > * [smmuv3] Add master->ats_invs scratch > > * [smmuv3] Add arm_smmu_cmdq_batch_issue() wrapper > > * [smmuv3] Force per-flush sync for has_ats batches > > * [smmuv3] Serialize STE.EATS and ats_broken updates > > * [smmuv3] Co-clear pending CMDQ_ERR from cmdq issuer > > * [smmuv3] Add invs and has_ats to arm_smmu_cmdq_batch > > * [smmuv3] Move arm_smmu_invs_for_each_entry to header > > * [smmuv3] Set master->ats_broken after clearing STE.EATS > > * [smmuv3] Issue CFGI_STE via arm_smmu_cmdq_issue_cmd_with_sync() > > * [smmuv3] Keep "smmu" pointer in arm_smmu_inv but add "master" for > > ATS > > Not check the detail yet, but this v4 more than doubles the number of > patches in v3. Are they all necessary to be in one series? any chance to > split to ease the review... Ah, sorry. Mostly these are dealing with racing and corner cases in the async design... Jason has suggested to drop quite a few things. So, I will respin a v5 that should be much smaller. Let's ignore this v4 for now. Thanks Nicolin