From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C30134753B for ; Sun, 10 May 2026 07:36:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778398584; cv=none; b=Rc17TR+OczSKUXumtjbZIFRw058KlJgmAP/vXKcdtoGTF6QiW34t5s2OJoOMbCkWY0i2zpm/26hZa5S+gjxroTElYCIsRtrBydk1J0aypcXiOXUTl/Ct735SvLtUentRc1UYnRbBX7xa0dlANPOSi7INUnlJnlSNqvmbUsPgXmI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778398584; c=relaxed/simple; bh=BPNo5pN9Nh0GjrveqNQIy/7dB1DQCVUuMTqlOt1ZeBk=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=GpnzpgWoGPc+RWDC55k6wb/YuwAoloJyguc4b+HvFPmzSPxJBy9xoXfX2qlUeak5oD+OfQRdXCsPfoLIrHGlOSP7sWsY9xNQ6LGaMonFFcjLwoz6uVc7m1OWgI5saA52SdpdRo96de8VXG9e56awx38oKe+Vg1GREFzTy3kbfI8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PCGcnOgR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PCGcnOgR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 87E05C2BCB8; Sun, 10 May 2026 07:36:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778398584; bh=BPNo5pN9Nh0GjrveqNQIy/7dB1DQCVUuMTqlOt1ZeBk=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=PCGcnOgRXDuMvtvCY2xs7f69k5bAD2hjMPy6D7dQb6oqVYLrWc6UtBd4DVVsAa9IO AUiqzWiHjZ0EqyPIiGtyndWuJHbEWUTxyAngADzSdeZ+t2kBDML3QJfxjxHLbyCMln EV9Qi5w/56HlHLaDt4zmaw35XM2t7O5PVnvoc3aCBjcWxNwE68gHipux7zNZPlTS/t y7Xm8e3UnoZe/N/ywiuKtlkiSrk4wUSrvHt36ks3yuXaHMAq8QwtvtE1/YG1HssPNy WpDwyDbnyUt1uNNXGP+wUf/eNp/JAYku7TSpOwvWmC64XtBvKg+sEusbPgk3M2GU3P SZzMJKkpjjj/Q== Date: Sun, 10 May 2026 13:06:20 +0530 From: Vinod Koul To: Cristian Ciocaltea Cc: Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov , kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups Message-ID: References: <20260227-hdptx-clk-fixes-v1-0-f998f2762d0f@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260227-hdptx-clk-fixes-v1-0-f998f2762d0f@collabora.com> On 27-02-26, 22:48, Cristian Ciocaltea wrote: > This series provides a set of bug fixes and cleanups for the Rockchip > Samsung HDPTX PHY driver. > > The first part of the series (i.e. PATCH 1 & 2) addresses clock rate > calculation and synchronization issues. Specifically, it fixes edge > cases where the PHY PLL is pre-programmed by an external component (like > a bootloader) or when changing the color depth (bpc) while keeping the > modeline constant. Because the Common Clock Framework .set_rate() > callback might not be invoked if the pixel clock remains unchanged, this > previously led to out-of-sync states between CCF and the actual HDMI PHY > configuration. > > The second part focuses on code cleanups and modernizing the register > access. Now that dw_hdmi_qp driver has fully switched to using > phy_configure(), we can drop the deprecated TMDS rate setup workarounds > and the restrict_rate_change flag logic. Finally, it refactors the > driver to consistently use standard bitfield macros. Sorry looks like I have missed to review this one. Can you please rebase on phy/fixes and send... Thanks -- ~Vinod