From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2688E4611C4 for ; Mon, 11 May 2026 17:37:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778521051; cv=none; b=lwJPefiQJxn8mCNzBzQuLAnbD8D2iN5GR6PrjdtrZY/V9+Ku9IQz4/Q0j9dkA6IwGzvc9d+5klPcCwL8ixwuM49GGGsYBmQu9h1mNF3l/ju/Lb638lypnzF5R3Fp5PaHMR4R0+OOqF2hh9J68gWUe5xWBh505z3LGayB4tkWcs8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778521051; c=relaxed/simple; bh=gfaMKAUI2+IeFh0GVFO1ztdIixh18hkmHJSnbfikQG4=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=LxNroi9iGd4IOCHsAL3J+iOnJgS6HVYF3wh9zyMKoSaTA0Y3Bo+2Uxwn4zHlwYRq7VLyKJJJIFkbiB7QO1YcgBQ9LBzJ3VOjaCUjG0bHF1DkHTaFsD9UpfbKpcpnMjFZcw8o7KpYHv11Wv1yU6WYMmL+3rcNLbOAqrvIOlW55PQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=XRvwV0G7; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="XRvwV0G7" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A9A4316A3; Mon, 11 May 2026 10:37:21 -0700 (PDT) Received: from arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 210FE3F85F; Mon, 11 May 2026 10:37:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778521046; bh=gfaMKAUI2+IeFh0GVFO1ztdIixh18hkmHJSnbfikQG4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=XRvwV0G7NbGQWHllpvk0PTIkmk9O4xsQAKVABIEhTjP/KdrPwIhCw2HAHu192UNzt ztRb7Ins8UmftzIzTXCNq2RwrdwtFhzy0jUxAMzHHJ6fAM5k0HZD52OK1XGZPPJCi3 Dp6aNwcAXp6jZIeV5yE6QQNAYPM17oaPZ568I+yc= Date: Mon, 11 May 2026 18:37:21 +0100 From: Catalin Marinas To: Jinjie Ruan Cc: will@kernel.org, punit.agrawal@oss.qualcomm.com, rafael.j.wysocki@intel.com, fengchengwen@huawei.com, chenl311@chinatelecom.cn, suzuki.poulose@arm.com, maz@kernel.org, timothy.hayes@arm.com, lpieralisi@kernel.org, mrigendra.chaubey@gmail.com, arnd@arndb.de, sudeep.holla@kernel.org, yangyicong@hisilicon.com, jic23@kernel.org, pierre.gondois@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, james.morse@arm.com Subject: Re: [PATCH v2] cpu/hotplug: Fix NULL kobject warning in cpuhp_smt_enable() Message-ID: References: <20260427023507.1247418-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260427023507.1247418-1-ruanjinjie@huawei.com> On Mon, Apr 27, 2026 at 10:35:07AM +0800, Jinjie Ruan wrote: > On arm64, when booting with `maxcpus` greater than the number of present > CPUs (e.g., QEMU -smp cpus=4,maxcpus=8), some CPUs are marked as 'present' > but have not yet been registered via register_cpu(). Consequently, > the per-cpu device objects for these CPUs are not yet initialized. [...] > Fix this by: > > 1. When booting with ACPI, checking the ACPI_MADT_ENABLED flag in the GICC > entry before calling set_cpu_present() during SMP initialization. > > 2. Properly managing the present mask in acpi_map_cpu() and > acpi_unmap_cpu() to support actual CPU hotplug events, This aligns with > other architectures like x86 and LoongArch. I had a chat with James earlier and IIUC the decision was to mark all CPUs present and the GIC must be fully initialised. But digging through the GICv3 code, I don't see it depending on cpu_present_mask but rather on the "always on" MADT GICR description. So I think it should be safe as long as we don't rely on the GICC gicr_base_address. But we should update Documentation/arch/arm64/cpu-hotplug.rst to no longer state that all online-capable vCPUs are marked as present by the kernel. (or maybe I misunderstood all this) -- Catalin