From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0B25477981; Mon, 11 May 2026 18:04:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778522675; cv=none; b=ngVS5WlbSnipA4QdUEzf/NIuUZLebbYQSYoUxGhcF6YUyPht1OkqAAkqI98Qcp01q/1BBsdJdVC3GVdAUKh0OqHGa7qsOQPg3ntB7L27pcjYw+czEdphstmy2cLUt4cOGpo2S9Td/6vrW3GifzBSSJoZympYry1GR/YRKqw2vA4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778522675; c=relaxed/simple; bh=5DDXjZwKmfb4MfZeTjaL80NJLxAk06ehb8Ek4HeG/mU=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=qQhvHxLaBcX+tVRqQRVZ4ng69vsvbNAOKSmgZjVVZym5XxwkKPaONG0daDgqG7WwcarU2Llbp6s10W+RR20jP7E8eoF8PpRLaCoTl2dKdTdKp8bVNjVHtCvL4h9mBQwAf3DF1US5kqpjKVJZlhIUZnXy3v6alwQMS07mMvtNGiQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ts1dnUUL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ts1dnUUL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 802CAC2BCB0; Mon, 11 May 2026 18:04:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778522675; bh=5DDXjZwKmfb4MfZeTjaL80NJLxAk06ehb8Ek4HeG/mU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ts1dnUULzU9zFWKjj9emjX/Tm1WS5BunucS/Ej7tr4CY95wvcWrQU3gCv+VavWxml WHgNdSfyK5t5hCN9muEQ+IIW0wdYUXZN3WHozApVrNCjgMM9zTpI9INMGfWLta2y2e f7MYrSJo/FZ1V7jkaZteAjpJLSQZmjDKJsBJwZ/jvQSnGOAJqeQXh3K0iNAp4aROyY e0qKaRJ6mSD2oaCmbGvzbD+3p8XvSb7lG9P5VhOR0Nw9YgzuwC5sNeIMyR+cwfGXrA WVPICvMe+EbtQole5FseQH0D9MVPUtwcNkEvnp2dXuTwlBHqrGwLHqKV7Pc+q+CfOt Uq2M23vqmjxXg== Date: Mon, 11 May 2026 13:04:31 -0500 From: Bjorn Andersson To: Alexander Koskovich Cc: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abel Vesa , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 4/4] pinctrl: qcom: eliza: Split QUP1_SE4 lanes Message-ID: References: <20260423-fix-eliza-pinctrl-v3-0-68b24893ae63@pm.me> <20260423-fix-eliza-pinctrl-v3-4-68b24893ae63@pm.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260423-fix-eliza-pinctrl-v3-4-68b24893ae63@pm.me> On Thu, Apr 23, 2026 at 04:43:46AM +0000, Alexander Koskovich wrote: > QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the > function name cannot be the same or the alternate function cannot > be selected. > > Split them up into individual lane functions so boards can specify. > This works, but it forces the DeviceTree source author to write a state per pin even though these are typically configured in pairs. What we did for hawi was to use the naming: qup1_se4_01 and qup1_se4_23 to express the two possible function pairs. I don't have any strong opinions on how to proceed with this platform (eliza), but I'm hoping we can follow the pair-wise scheme going forward. Regards, Bjorn > Signed-off-by: Alexander Koskovich > --- > drivers/pinctrl/qcom/pinctrl-eliza.c | 30 ++++++++++++++++++++++++------ > 1 file changed, 24 insertions(+), 6 deletions(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pinctrl-eliza.c > index 8f74756771b8..40e263e35b45 100644 > --- a/drivers/pinctrl/qcom/pinctrl-eliza.c > +++ b/drivers/pinctrl/qcom/pinctrl-eliza.c > @@ -568,7 +568,10 @@ enum eliza_functions { > msm_mux_qup1_se2_l3_mira, > msm_mux_qup1_se2_l3_mirb, > msm_mux_qup1_se3, > - msm_mux_qup1_se4, > + msm_mux_qup1_se4_l0, > + msm_mux_qup1_se4_l1, > + msm_mux_qup1_se4_l2, > + msm_mux_qup1_se4_l3, > msm_mux_qup1_se5, > msm_mux_qup1_se6, > msm_mux_qup1_se6_l1_mira, > @@ -1017,8 +1020,20 @@ static const char *const qup1_se3_groups[] = { > "gpio44", "gpio45", "gpio46", "gpio47", > }; > > -static const char *const qup1_se4_groups[] = { > - "gpio36", "gpio37", "gpio37", "gpio36", > +static const char *const qup1_se4_l0_groups[] = { > + "gpio36", > +}; > + > +static const char *const qup1_se4_l1_groups[] = { > + "gpio37", > +}; > + > +static const char *const qup1_se4_l2_groups[] = { > + "gpio37", > +}; > + > +static const char *const qup1_se4_l3_groups[] = { > + "gpio36", > }; > > static const char *const qup1_se5_groups[] = { > @@ -1321,7 +1336,10 @@ static const struct pinfunction eliza_functions[] = { > MSM_PIN_FUNCTION(qup1_se2_l3_mira), > MSM_PIN_FUNCTION(qup1_se2_l3_mirb), > MSM_PIN_FUNCTION(qup1_se3), > - MSM_PIN_FUNCTION(qup1_se4), > + MSM_PIN_FUNCTION(qup1_se4_l0), > + MSM_PIN_FUNCTION(qup1_se4_l1), > + MSM_PIN_FUNCTION(qup1_se4_l2), > + MSM_PIN_FUNCTION(qup1_se4_l3), > MSM_PIN_FUNCTION(qup1_se5), > MSM_PIN_FUNCTION(qup1_se6), > MSM_PIN_FUNCTION(qup1_se6_l1_mira), > @@ -1418,8 +1436,8 @@ static const struct msm_pingroup eliza_groups[] = { > [33] = PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _, _, _, _, _), > [34] = PINGROUP(34, qup1_se1, qup1_se5, tb_trig_sdc1, ddr_bist_start, qdss_gpio_tracedata, _, _, _, _, _, _), > [35] = PINGROUP(35, qup1_se1, qup1_se5, tb_trig_sdc2, gcc_gp2, qdss_gpio_tracedata, _, _, _, _, _, _), > - [36] = PINGROUP(36, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _), > - [37] = PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _), > + [36] = PINGROUP(36, qup1_se4_l0, qup1_se4_l3, ibi_i3c, _, _, _, _, _, _, _, _), > + [37] = PINGROUP(37, qup1_se4_l1, qup1_se4_l2, ibi_i3c, _, _, _, _, _, _, _, _), > [38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _), > [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _), > [40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6_l3_mira, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _), > > -- > 2.53.0 > >