From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAAE73C8C69 for ; Tue, 12 May 2026 15:45:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778600728; cv=none; b=Wa06ylfzBJK3GYkdtzRo2iL/1m/oAreIhi7hXng6BHBr4waTEhOy3+zb3yQWAgtJL1wBCDro6clmxQ7V3acq6az5pYPnSoz7pOaOvURhXkw3LeCHptlE95+Md0cMUaIpgyrwparBRL4Ffde9keukYO+B+dcRJB/U0RlYZd3C3sE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778600728; c=relaxed/simple; bh=29A/M4xYVUS372XJHCDISmn4w9ov/gKfjHEVp9qR1aE=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=O0dpku5w4C8RnxIdx0scI1WkVaK6sIoSbDx34ugc6xQ3zLfcehrygZZ/PIyCypITAJC+2dGIpiQ0X61li+e4q4uOHl2ojtm7+NoPi1HaXtEChmn1NJ1VskdFbrqaGooFCf6MA3iFz/frHOTwwvyORylWQr+OxuERb19PifhDF1s= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=WXaK6T8K; dkim=pass (2048-bit key) header.d=redhat.com header.i=@redhat.com header.b=bQDQBi/r; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="WXaK6T8K"; dkim=pass (2048-bit key) header.d=redhat.com header.i=@redhat.com header.b="bQDQBi/r" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1778600726; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=F/Rj20yJzwwrc5IUSlJqObsXWAOLzLYrlkLUj5Fyb3E=; b=WXaK6T8KCV+kQ+S3LeFQQT7q6wF566sWDYpGF1VGyCOwGHgJlTuyf2ys3uzBo9+gNbQqQw q50t27Ocj+RVJnURG7RiBB8+hkwd8U0egAAM8F4WGjG2QY0aNbTQj9KWt6ghKMkU0D3T1e ChEEUZbwhMH1S09OX3JZERaqqsRykV8= Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-283-PgO0PSuAOaGIB4ljS2ozUg-1; Tue, 12 May 2026 11:45:22 -0400 X-MC-Unique: PgO0PSuAOaGIB4ljS2ozUg-1 X-Mimecast-MFC-AGG-ID: PgO0PSuAOaGIB4ljS2ozUg_1778600722 Received: by mail-qk1-f199.google.com with SMTP id af79cd13be357-90e311df56eso107191385a.1 for ; Tue, 12 May 2026 08:45:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=google; t=1778600722; x=1779205522; darn=vger.kernel.org; h=user-agent:in-reply-to:content-disposition:mime-version:references :message-id:subject:cc:to:from:date:from:to:cc:subject:date :message-id:reply-to; bh=F/Rj20yJzwwrc5IUSlJqObsXWAOLzLYrlkLUj5Fyb3E=; b=bQDQBi/rcQGU3rwhCC9Q0IWh8Uq123zdU0XsfZKJCJWEJhhZqEnOIiTWOnf/nl0NI9 uZVP77Jmj68eQFbXu36zSGHSqS4lYFFjDkpnfKL/++qg5rcF9N2qtrlhGH9laiU+5Da0 3DiS9AuVLLqhq6+USAYd1hRXM7BBxgSH+LyBqiVuOWBdJQMOSaTyr8xoi2r+Gqe5ViRA BxcjSQNSCYXGIfe+EBV3OiZVPcanlfwOH9f4DiYEm8q++JHpunpIjv2aDA3SR1ueXNJp XkUEPZyKOjxR4JxKmrYkHeT+ntLL51BONLEIlnIv4n+b1NU9VEPToA8apZf6SUYHvyqh TOOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778600722; x=1779205522; h=user-agent:in-reply-to:content-disposition:mime-version:references :message-id:subject:cc:to:from:date:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=F/Rj20yJzwwrc5IUSlJqObsXWAOLzLYrlkLUj5Fyb3E=; b=j29bzjRtBSN5rFN0KPg2Hh5a4GgdhwE0C5t6WJDyH3M2ewOIRRLVeL1TI1eqWnztZ5 IFBTpMscJtdVXmJcMfJ65OoKaanZFdUYiMH6TfP1Ellz4vOwGZKHKVlBHq8c1fWwIKeX qrlp6XRrBNZ+5WTWnniWfHhkvt+MA5FDXXkLVGvYgugSsE9hugma3wHn6lFAWkNOP9nv 6dhLvBgelCHYMTkFExZmRW0QbsOVMORmVncePxtplGMj6OprxvgRvwN/bprL/DqVp6qd ug924J1dx+QWdZsP/W9gPyTklb08H89efTUlnchECJWl6EMcnNUvk26rGcCe60+ovdCg I+mA== X-Forwarded-Encrypted: i=1; AFNElJ8QXQCSbzhvg3L8dNyyPbPz0135RdJ5pPkFrggdrvuuiYjjdBjdexWyiVFbcTRfwNIHtFN8V1h1AAXh2Qo=@vger.kernel.org X-Gm-Message-State: AOJu0YzLkfEVOZvaSvfEZH2ZlUW7+FVZFZZ4rfUVosbD3E1I/DKa9DRh p88N6/86tblPpkbpa0BKltXYCltSDEqjxFWZuyrpr6uW0HQPktikJ1lGjRWRNTl4NqV1uz5qzJX boTkRrCbVUDBNYXEA5I/otkP6+y1N3ZL63rwFCr1Txclr9tetNJMNJebJXUk6X22bZw== X-Gm-Gg: Acq92OGxePeZ5QTbadqHBO9vrAHL2zDvTfb9pYR9PfWWZR33qt22LvTP/Fg797/RqHB aiqBIvh1fofLhJVSoQueO8oXtm11UQkbr7PDxa4s8O0MnQjOu1u304B3LHkhc1qOCadzewP6u8M LHu1JTulA3PwYn/aBaFcNC7/Q+rjqkRHsN4Mv13bbvCZqD5la0R0/SAX6Z2AzQALm9UOAnBY1g9 Q0KBbBjrtxwYvGN+KsRElc78NhVy7lQURJ947gI25b3xyI0LPChq0tCN7JbmfLg2lQji1Q0gzTj 3nv98uG8UzjB9c0J66oggmpquPI0QDntpG21iYk+j7fjPjB017WaDuJg3YZeVxRMHNIFzMIAmdK 7KsC//WkLzbH4ILCcu6I/6I8Qwv0v2um/Wn4gYu9ZJcJtsqwzRX9F1EtT X-Received: by 2002:a05:620a:370f:b0:8f2:31f3:975a with SMTP id af79cd13be357-90cb6efb828mr596038585a.18.1778600721831; Tue, 12 May 2026 08:45:21 -0700 (PDT) X-Received: by 2002:a05:620a:370f:b0:8f2:31f3:975a with SMTP id af79cd13be357-90cb6efb828mr596027585a.18.1778600721164; Tue, 12 May 2026 08:45:21 -0700 (PDT) Received: from redhat.com (c-73-183-52-120.hsd1.pa.comcast.net. [73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8fc2c91b976sm3502993885a.39.2026.05.12.08.45.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2026 08:45:20 -0700 (PDT) Date: Tue, 12 May 2026 11:45:18 -0400 From: Brian Masney To: Xuyang Dong Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, p.zabel@pengutronix.de, huangyifeng@eswincomputing.com, benoit.monin@bootlin.com, ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com Subject: Re: [PATCH v4 2/3] clk: eswin: Add eic7700 HSP clock driver Message-ID: References: <20260512020432.671-1-dongxuyang@eswincomputing.com> <20260512020747.993-1-dongxuyang@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260512020747.993-1-dongxuyang@eswincomputing.com> User-Agent: Mutt/2.3.1 (2026-03-20) Hi Xuyang, On Tue, May 12, 2026 at 10:07:47AM +0800, Xuyang Dong wrote: > Add driver for the ESWIN EIC7700 high-speed peripherals system > clock controller and register an auxiliary device for system > reset controller which is named as "hsp-reset". > > Signed-off-by: Xuyang Dong > --- > drivers/clk/eswin/Kconfig | 12 + > drivers/clk/eswin/Makefile | 1 + > drivers/clk/eswin/clk-eic7700-hsp.c | 338 ++++++++++++++++++++++++++++ > 3 files changed, 351 insertions(+) > create mode 100644 drivers/clk/eswin/clk-eic7700-hsp.c > > diff --git a/drivers/clk/eswin/Kconfig b/drivers/clk/eswin/Kconfig > index 0406ec499ec9..e6cc2a407bac 100644 > --- a/drivers/clk/eswin/Kconfig > +++ b/drivers/clk/eswin/Kconfig > @@ -13,3 +13,15 @@ config COMMON_CLK_EIC7700 > SoC. The clock controller generates and supplies clocks to various > peripherals within the SoC. > Say yes here to support the clock controller on the EIC7700 SoC. > + > +config COMMON_CLK_EIC7700_HSP > + tristate "EIC7700 HSP Clock Driver" > + depends on ARCH_ESWIN || COMPILE_TEST > + select AUXILIARY_BUS > + select COMMON_CLK_EIC7700 > + select RESET_EIC7700_HSP if RESET_CONTROLLER > + help > + This driver provides support for clock controller on ESWIN EIC7700 > + HSP. The clock controller generates and supplies clocks to high > + speed peripherals within the SoC. > + Say yes here to support the clock controller on the EIC7700 HSP. > diff --git a/drivers/clk/eswin/Makefile b/drivers/clk/eswin/Makefile > index 4a7c2af82164..21a09a3396df 100644 > --- a/drivers/clk/eswin/Makefile > +++ b/drivers/clk/eswin/Makefile > @@ -6,3 +6,4 @@ > obj-$(CONFIG_COMMON_CLK_ESWIN) += clk.o > > obj-$(CONFIG_COMMON_CLK_EIC7700) += clk-eic7700.o > +obj-$(CONFIG_COMMON_CLK_EIC7700_HSP) += clk-eic7700-hsp.o > diff --git a/drivers/clk/eswin/clk-eic7700-hsp.c b/drivers/clk/eswin/clk-eic7700-hsp.c > new file mode 100644 > index 000000000000..0d5bd5b705dc > --- /dev/null > +++ b/drivers/clk/eswin/clk-eic7700-hsp.c > @@ -0,0 +1,338 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd.. > + * All rights reserved. > + * > + * ESWIN EIC7700 HSP Clock Driver > + * > + * Authors: Xuyang Dong > + */ > + > +#include > +#include > +#include > +#include > + > +#include > + > +#include "common.h" > + > +#define EIC7700_HSP_SATA_REG 0x300 > +#define EIC7700_HSP_MSHC0_REG 0x510 > +#define EIC7700_HSP_MSHC1_REG 0x610 > +#define EIC7700_HSP_MSHC2_REG 0x710 > +#define EIC7700_HSP_USB0_REG 0x800 > +#define EIC7700_HSP_USB0_REF_REG 0x83c > +#define EIC7700_HSP_USB1_REG 0x900 > +#define EIC7700_HSP_USB1_REF_REG 0x93c > + > +#define USB_REF_XTAL24M 0x2a > +#define EIC7700_HSP_NR_CLKS (EIC7700_HSP_CLK_GATE_SATA + 1) > + > +struct eic7700_hsp_clk_gate { > + struct clk_hw hw; > + unsigned int id; > + struct regmap *regmap; > + unsigned int reg; > + unsigned int ref_reg; > + const char *name; > + const struct clk_parent_data *parent_data; > + unsigned long flags; > + unsigned int offset; > + unsigned int ref_offset; > + u8 bit_idx; > +}; > + > +static const struct regmap_config eic7700_hsp_regmap_config = { > + .reg_bits = 32, > + .val_bits = 32, > + .max_register = 0x1ffc, > + .reg_stride = 4, > + .fast_io = true, > + .use_raw_spinlock = true, > +}; > + > +static inline struct eic7700_hsp_clk_gate *to_gate_clk(struct clk_hw *hw) > +{ > + return container_of(hw, struct eic7700_hsp_clk_gate, hw); > +} > + > +#define EIC7700_HSP_GATE(_id, _name, _pdata, _flags, _offset, _idx, \ > + _ref_offset) \ > + { \ > + .id = _id, \ > + .name = _name, \ > + .parent_data = _pdata, \ > + .flags = _flags, \ > + .offset = _offset, \ > + .ref_offset = _ref_offset, \ > + .bit_idx = _idx, \ > + } > + > +static void hsp_clk_gate_endisable(struct clk_hw *hw, bool enable) > +{ > + struct eic7700_hsp_clk_gate *gate = to_gate_clk(hw); > + > + if (enable) { > + /* > + * Hardware bug: The USB reference clock must be 24MHz. > + * The default register value after reset is invalid. > + * Workaround: Rewrite the correct value before enabling > + * the USB gate clock. > + */ > + regmap_update_bits(gate->regmap, gate->ref_reg, 0x3f, > + USB_REF_XTAL24M); > + } > + regmap_assign_bits(gate->regmap, gate->reg, BIT(gate->bit_idx), enable); > +} > + > +static int hsp_clk_gate_enable(struct clk_hw *hw) > +{ > + hsp_clk_gate_endisable(hw, true); > + > + return 0; > +} > + > +static void hsp_clk_gate_disable(struct clk_hw *hw) > +{ > + hsp_clk_gate_endisable(hw, false); > +} > + > +static int hsp_clk_gate_is_enabled(struct clk_hw *hw) > +{ > + struct eic7700_hsp_clk_gate *gate = to_gate_clk(hw); > + unsigned int val; > + > + regmap_read(gate->regmap, gate->reg, &val); > + > + return !!(val & BIT(gate->bit_idx)); If the regmap_read() fails, then val will be uninitialized. With that fixed: Reviewed-by: Brian Masney