From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA28F311977 for ; Fri, 22 May 2026 18:19:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779473945; cv=none; b=IGb3uHK6245ODipeOeq/ucqZV+nQvKEIix+SEpmlP7VHAN1W77NGJqWILp5ey90Ni+qOQJH0dkNz7pScpNq+l6/qqD8Xpb+dMz+01ElnTvG5mn9l6nQ26i/gJWxFrE1mEE0IeFrgdd0FuIg4N6rCFl0jNAkMUWL3y9DmI6j73LQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779473945; c=relaxed/simple; bh=rQ4Y7nagtCKEmKniU+R5AbpYhu/DJlNiFJo4ePL8mrU=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Iuom3b3HYUYCKJDvAw9bnth3PDssORJs8TxcPJDmSS2xtGXm00ARV30ciVCDONmRyr6K3YaWpg1v8HdGBNthNE5mWIpjGY2wDTZdTXSTFBu/zghK6HvLjZJra9InUdMZFAS0Z2yx/aJFxrmSXh1pCXmqDNienlfLUQQIm5IDFFY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XHFc1E90; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XHFc1E90" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779473944; x=1811009944; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=rQ4Y7nagtCKEmKniU+R5AbpYhu/DJlNiFJo4ePL8mrU=; b=XHFc1E90J4M2DXXbacc3BH7mB7TAoO5YDAKcVwbM4DXGbstYgvX5gMRY FzWxl7GhqbRowsT3pKub3Rxx5VyFbk7QgelRfI2Mp9PzRMBKeGmz3+fF0 BqmRXBRxsskid1Kk/SVqGdVgiOgq70Rds/4z4ttYbX2GLJlJg33bvA+Fv QSKjiOs4zetJpK28XM+s8WnnlHny3yFGGrim/pddbgd7DyoIvb3sAb1aS qRUnRixirj6FcP8ZmAZ0aHARCr0rLr4hL7wsilkrwdo9+2fhaPwI7LBOu THb2hJ2PLnktH+vrgp9Xmrm3MXYYcJMmyn4FzZjqRehZFwX7DgDz+c8Wk w==; X-CSE-ConnectionGUID: uKIUff5ZRjmmLhLGLU0LkQ== X-CSE-MsgGUID: SYdfBd/JSpSki+j4A+O6cg== X-IronPort-AV: E=McAfee;i="6800,10657,11794"; a="80441107" X-IronPort-AV: E=Sophos;i="6.24,162,1774335600"; d="scan'208";a="80441107" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2026 11:19:03 -0700 X-CSE-ConnectionGUID: QK9eXneaQOKRzUxCnO33cA== X-CSE-MsgGUID: CLl1Hd9sRvuOITV2TE1G0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,162,1774335600"; d="scan'208";a="271327221" Received: from amilburn-desk.amilburn-desk (HELO localhost) ([10.245.244.187]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2026 11:19:00 -0700 Date: Fri, 22 May 2026 21:18:56 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Leandro Ribeiro Cc: dri-devel@lists.freedesktop.org, airlied@gmail.com, daniels@collabora.com, jani.nikula@linux.intel.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, pekka.paalanen@collabora.com, simona@ffwll.ch, tzimmermann@suse.de, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 2/2] drm: ensure blend mode supported if alpha exposed Message-ID: References: <20260518175429.80615-1-leandro.ribeiro@collabora.com> <20260518175429.80615-3-leandro.ribeiro@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260518175429.80615-3-leandro.ribeiro@collabora.com> X-Patchwork-Hint: comment Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland On Mon, May 18, 2026 at 02:54:29PM -0300, Leandro Ribeiro wrote: > Before "drm/drm_blend: allow blend mode property without PREMULTI", > userspace would have to assume that only PREMULTI was supported by > drivers that didn't expose the blend mode property. But now userspace > shouldn't relly on that, as they can't count with drivers always > supporting PREMULTI. > > Error out if a driver expose alpha property or pixel formats with alpha > and does not expose the blend mode property. This way userspace don't > have to guess. Drivers that hit such error must be fixed. I don't think the error handling is a good idea. It's just another completely untested error path that is more or less guaranteed to break eventually. So IMO just WARN and plow ahead like we do for everything else there. > > Signed-off-by: Leandro Ribeiro > --- > drivers/gpu/drm/drm_crtc_internal.h | 2 +- > drivers/gpu/drm/drm_drv.c | 7 ++++-- > drivers/gpu/drm/drm_mode_config.c | 37 +++++++++++++++++++++++++++-- > 3 files changed, 41 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc_internal.h > index c09409229644..2a4862202496 100644 > --- a/drivers/gpu/drm/drm_crtc_internal.h > +++ b/drivers/gpu/drm/drm_crtc_internal.h > @@ -95,7 +95,7 @@ int drm_mode_setcrtc(struct drm_device *dev, > /* drm_mode_config.c */ > int drm_modeset_register_all(struct drm_device *dev); > void drm_modeset_unregister_all(struct drm_device *dev); > -void drm_mode_config_validate(struct drm_device *dev); > +int drm_mode_config_validate(struct drm_device *dev); > > /* drm_modes.c */ > const char *drm_get_mode_status_name(enum drm_mode_status status); > diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c > index 985c283cf59f..def78046a963 100644 > --- a/drivers/gpu/drm/drm_drv.c > +++ b/drivers/gpu/drm/drm_drv.c > @@ -1059,8 +1059,11 @@ int drm_dev_register(struct drm_device *dev, unsigned long flags) > const struct drm_driver *driver = dev->driver; > int ret; > > - if (!driver->load) > - drm_mode_config_validate(dev); > + if (!driver->load) { > + ret = drm_mode_config_validate(dev); > + if (ret) > + return ret; > + } > > WARN_ON(!dev->managed.final_kfree); > > diff --git a/drivers/gpu/drm/drm_mode_config.c b/drivers/gpu/drm/drm_mode_config.c > index 66f7dc37b597..18c6b5707532 100644 > --- a/drivers/gpu/drm/drm_mode_config.c > +++ b/drivers/gpu/drm/drm_mode_config.c > @@ -674,16 +674,45 @@ static void validate_encoder_possible_crtcs(struct drm_encoder *encoder) > encoder->possible_crtcs, crtc_mask); > } > > -void drm_mode_config_validate(struct drm_device *dev) > +static int plane_alpha_require_blend_mode(struct drm_plane *plane) > +{ > + struct drm_device *dev = plane->dev; > + const struct drm_format_info *fmt; > + u32 i; > + > + /* blend mode property supported, no need to check anything */ > + if (plane->blend_mode_property) > + return 0; > + > + if (plane->alpha_property) { > + drm_err(dev, "[PLANE:%d:%s] alpha property exposed but blend mode not setup", > + plane->base.id, plane->name); > + return -EINVAL; > + } > + > + for (i = 0; i < plane->format_count; i++) { > + fmt = drm_format_info(plane->format_types[i]); > + if (fmt->has_alpha) { > + drm_err(dev, "[PLANE:%d:%s] pixel format with alpha exposed but blend mode not setup", > + plane->base.id, plane->name); > + return -EINVAL; > + } > + } > + > + return 0; > +} > + > +int drm_mode_config_validate(struct drm_device *dev) > { > struct drm_encoder *encoder; > struct drm_crtc *crtc; > struct drm_plane *plane; > u32 primary_with_crtc = 0, cursor_with_crtc = 0; > unsigned int num_primary = 0; > + int ret = 0; > > if (!drm_core_check_feature(dev, DRIVER_MODESET)) > - return; > + return ret; > > drm_for_each_encoder(encoder, dev) > fixup_encoder_possible_clones(encoder); > @@ -732,9 +761,13 @@ void drm_mode_config_validate(struct drm_device *dev) > drm_for_each_plane(plane, dev) { > if (plane->type == DRM_PLANE_TYPE_PRIMARY) > num_primary++; > + > + ret |= plane_alpha_require_blend_mode(plane); > } > > WARN(num_primary != dev->mode_config.num_crtc, > "Must have as many primary planes as there are CRTCs, but have %u primary planes and %u CRTCs", > num_primary, dev->mode_config.num_crtc); > + > + return ret; > } > -- > 2.54.0 -- Ville Syrjälä Intel