From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0AB2B239567 for ; Thu, 28 May 2026 13:46:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779976011; cv=none; b=JWrqDFQVgT5e2yVr4+W1hQm5nT9olLzWNRJTpwp3+V31BWrCvUtF+cR4j3XX1y68OE3tR3v+w415dhQHGjNj6bkPgMk/gnvhlpGY6jRbpjeE5TbudpMv9zJCDp3yTmg8D7IDTKyi5nnRW2d2l8H+BxKHd/ENHkP9/vH7i+1qcnU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779976011; c=relaxed/simple; bh=4nxponVIkOLb70m0Mgu402MDpADCLWcz77FHIclzLpM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=kl0lwjwKcEnKVOjvQ1B6dInG/9mslATweI7rVnMG2Xr38JD9B5WNICsT6XnC9qtvH7PIK8x/M7Titd7OrJWbRji/MpwuNLv8k8oPrT3X+Dv3Q4IEd7N4bYZ9eMEnXhHzOcOctKMDCCou3f+EnYWwEYyoP6fGNnzX+keUNek0yJk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=X4ThdaIG; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="X4ThdaIG" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 77C5C4402; Thu, 28 May 2026 06:46:44 -0700 (PDT) Received: from e129823.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 201923F632; Thu, 28 May 2026 06:46:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1779976009; bh=4nxponVIkOLb70m0Mgu402MDpADCLWcz77FHIclzLpM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=X4ThdaIGWzSUqrfe1ax7ZT87GKkBfa/VEc0dJb+qZTihywfTCY/CnF5/FTvlxHC9F lUhKHoVY3IXASUr04y4kqPfISa9M5GRNWf7afRapCmJtIinj6khKjicZl5B147+YXq WhxODfsa6beHZolWMi+Hn+G4YsFVPsxURa7cqpyw= Date: Thu, 28 May 2026 14:46:45 +0100 From: Yeoreum Yun To: Leo Yan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, jie.gan@oss.qualcomm.com Subject: Re: [PATCH v7 05/13] coresight: etm4x: exclude ss_status from drvdata->config Message-ID: References: <20260519154812.254884-1-yeoreum.yun@arm.com> <20260519154812.254884-6-yeoreum.yun@arm.com> <20260528133057.GD101133@e132581.arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260528133057.GD101133@e132581.arm.com> Hi Leo, > On Tue, May 19, 2026 at 04:48:04PM +0100, Yeoreum Yun wrote: > > [...] > > > @@ -571,11 +571,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > > etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); > > > > for (i = 0; i < caps->nr_ss_cmp; i++) { > > - /* always clear status bit on restart if using single-shot */ > > + /* always clear status and pending bits on restart if using single-shot */ > > if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) > > - config->ss_status[i] &= ~TRCSSCSRn_STATUS; > > + drvdata->ss_status[i] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING); > > etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); > > - etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); > > + etm4x_relaxed_write32(csa, drvdata->ss_status[i], TRCSSCSRn(i)); > > if (etm4x_sspcicrn_present(drvdata, i)) > > etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); > > } > > @@ -772,6 +772,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, > > /* Clear configuration from previous run */ > > memset(config, 0, sizeof(struct etmv4_config)); > > > > + > > Unexpected new line? Oops. I'll remove it. > > > @@ -1497,8 +1498,9 @@ static void etm4_init_arch_data(void *info) > > */ > > caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); > > for (i = 0; i < caps->nr_ss_cmp; i++) { > > - drvdata->config.ss_status[i] = > > - etm4x_relaxed_read32(csa, TRCSSCSRn(i)); > > + drvdata->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i)); > > + drvdata->ss_status[i] &= (TRCSSCSRn_PC | TRCSSCSRn_DV | > > + TRCSSCSRn_DA | TRCSSCSRn_INST); > > Since etm4_enable_hw() clears the TRCSSCSRn_STATUS and > TRCSSCSRn_PENDING bits every time, here is no need to clear the > status bits during probe. > > In the future, we may want to preserve the status within a session and > clear it only when starting a new session. Clearing the status bits here > still cannot handle stale status across multiple sessions, so we can > defer this improvement for later. Yes. That would require near future as we discussed in offline. but the at the initialisation perspective, it should ignore those bits since that would be random value after reset. So, I'll remain it as it is. -- Sincerely, Yeoreum Yun