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[34.124.234.44]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2beff36894dsm28676365ad.37.2026.05.28.08.24.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 08:24:47 -0700 (PDT) Date: Thu, 28 May 2026 15:24:40 +0000 From: Pranjal Shrivastava To: Nicolin Chen Cc: jgg@nvidia.com, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, bhelgaas@google.com, baolu.lu@linux.intel.com, kevin.tian@intel.com, miko.lenczewski@arm.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, dan.j.williams@intel.com, jonathan.cameron@huawei.com, vsethi@nvidia.com, linux-cxl@vger.kernel.org, nirmoyd@nvidia.com Subject: Re: [PATCH v6 3/3] iommu/arm-smmu-v3: Allow ATS to be always on Message-ID: References: <18bb6f421b3be891caa8f1fb50f3a4d56b52d5be.1779392420.git.nicolinc@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <18bb6f421b3be891caa8f1fb50f3a4d56b52d5be.1779392420.git.nicolinc@nvidia.com> On Thu, May 21, 2026 at 01:34:22PM -0700, Nicolin Chen wrote: > When a device's default substream attaches to an identity domain, the SMMU > driver currently sets the device's STE between two modes: > > Mode 1: Cfg=Translate, S1DSS=Bypass, EATS=1 > Mode 2: Cfg=bypass (EATS is ignored by HW) > > When there is an active PASID (non-default substream), mode 1 is used. And > when there is no PASID support or no active PASID, mode 2 is used. > > The driver will also downgrade an STE from mode 1 to mode 2, when the last > active substream becomes inactive. > > However, there are PCIe devices that demand ATS to be always on. For these > devices, their STEs have to use the mode 1 as HW ignores EATS with mode 2. > > Change the driver accordingly: > - always use the mode 1 > - never downgrade to mode 2 > - allocate and retain a CD table (see note below) > > Note that these devices might not support PASID, i.e. doing non-PASID ATS. > In such a case, the ssid_bits is set to 0. However, s1cdmax must be set to > a !0 value in order to keep the S1DSS field effective. Thus, when a master > requires ats_always_on, set its s1cdmax to at least 1, meaning that the CD > table will have a dummy entry (SSID=1) that will never be used. > > Now for these devices, arm_smmu_cdtab_allocated() will always return true, > v.s. false prior to this change. When its default substream is attached to > an IDENTITY domain, its first CD is NULL in the table, which is a totally > valid case. Thus, add "!master->ats_always_on" to the condition. > > Reviewed-by: Jonathan Cameron > Tested-by: Nirmoy Das > Acked-by: Nirmoy Das > Reviewed-by: Jason Gunthorpe > Reviewed-by: Kevin Tian > Reviewed-by: Dave Jiang > Signed-off-by: Nicolin Chen > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 81 ++++++++++++++++++--- > 2 files changed, 73 insertions(+), 9 deletions(-) > Reviewed-by: Pranjal Shrivastava > > +static int arm_smmu_master_prepare_ats(struct arm_smmu_master *master) > +{ > + bool s1p = master->smmu->features & ARM_SMMU_FEAT_TRANS_S1; > + unsigned int stu = __ffs(master->smmu->pgsize_bitmap); > + struct pci_dev *pdev; > + int ret; > + > + if (!dev_is_pci(master->dev)) > + return 0; > + pdev = to_pci_dev(master->dev); > + > + if (!arm_smmu_ats_supported(master)) { > + if (pci_ats_required(pdev)) { > + dev_err_once(master->dev, "SMMU doesn't support ATS\n"); > + return -EOPNOTSUPP; > + } > + return 0; > + } > + > + ret = pci_prepare_ats(pdev, stu); > + if (ret || !pci_ats_required(pdev)) > + return ret; > + > + /* > + * S1DSS is required for ATS to be always on for identity domain cases. > + * However, the S1DSS field is ignored if !IDR0_S1P or !IDR1_SSIDSIZE. > + */ > + if (!s1p || !master->smmu->ssid_bits) { > + dev_err_once(master->dev, > + "SMMU doesn't support ATS to be always on\n"); > + return -EOPNOTSUPP; > + } > + > + master->ats_always_on = true; > + > + return arm_smmu_alloc_cd_tables(master); Nit: I'm not sure if I'm getting this right, are we saying we *need* to allocate CDs for CXL.cache cases in the probe itself because STE.EATS requires Config=Translate with S1DSS in bypass? Does this imply that active transactions can be occurring *before* the first domain attach? Are Thanks, Praan