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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-3965b3cb6fesm14245011fa.14.2026.05.31.03.25.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 May 2026 03:25:33 -0700 (PDT) Date: Sun, 31 May 2026 12:25:30 +0200 From: Marcus Folkesson To: Wolfram Sang Cc: Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti , Andy Shevchenko , Bartosz Golaszewski , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v9 5/5] docs: i2c: i2c-topology: add section about bus speed Message-ID: References: <20260324-i2c-mux-v9-0-5292b0608243@gmail.com> <20260324-i2c-mux-v9-5-5292b0608243@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: Hi, On Tue, May 26, 2026 at 09:48:13PM +0200, Wolfram Sang wrote: >=20 > > +Multiple muxes in series > > +-------------------------- > > + > > +When multiple muxes are used in series the same rules applies. > > + > > +Transfers to D3 may interleave between select-transfer-deselect to D1,= which > > +results that the bus speed to D2 or D3 will be at 100KHz. > > + > > +Transfers to D2 may interleave between select-transfer-deselect to D1,= which > > +results in that the bus speed to D1 may be at 400kHz as the transfer t= o D2 > > +will set the bus speed to before the transfer to D1 starts. > > + > > +This is probably a bad topology :: >=20 > In documentation, we probably shouldn't say "probably" ;) Answer in next mail. >=20 > > + > > + .----------. 400kHz .----------. 100kHz .--------. > > + .--------.400kHz | mux- |--------| mux- |--------| dev D1 | > > + | root |--+----| locked | 400kHz | locked | '--------' > > + '--------' | | mux M1 |--. | mux M2 | > > + | '----------' | '----------' > > + | .--------. | .--------. > > + '--| dev D3 | '--| dev D2 | > > + '--------' '--------' >=20 > 400kHz leaking to a 100kHz device is bad. I guess we cannot do much > about it here because the bus speed is a board specific parameter... >=20 > > +Idle state > > +----------- > > + > > +Muxes have an idle state, which is the state the channels are put into= when no channel > > +is active. The state is typically one of the following: > > + > > +- All channels are disconnected > > +- The last selected channel is left as-is > > +- A predefined channel is selected > > + > > +Muxes that support an idle state where all channels are disconnected a= re preferred when using > > +different bus speeds. Otherwise high bus speeds may "leak" through to = devices that > > +may not support that higher speed. > > + > > +Consider the following example: :: > > + > > + .----------. 100kHz .--------. > > + .--------. 400kHz | mux- |--------| dev D1 | > > + | root |--+-----| locked | '--------' > > + '--------' | | mux M1 |--. 400kHz .--------. > > + | '----------' '--------| dev D2 | > > + | .--------. '--------' > > + '--| dev D3 | > > + '--------' > > + > > +If the idle state of M1 is: > > + > > +- All channels disconnected: No problem, D1 and D2 are not affected by= communication > > + to D3. > > +- Last selected channel: Problem if D1 was the last selected channel. = High speed > > + communication to D3 will be "leaked" to D1. > > +- Predefined channel: Problem if the predefined channel D1. Set predef= ined channel > > + to D2 as D2 may handle 400kHz. >=20 > ... unlike here. We have MUX_IDLE_AS_IS and MUX_IDLE_DISCONNECT defined > already. And I'd think we should only allow bus speed switching for > MUX_IDLE_DISCONNECT to avoid out-of-spec scenarios. Opinions? Answer in next mail. >=20 > > +Supported controllers > > +----------------------- > > + > > +Not all I2C controllers support setting the bus speed dynamically. > > +At the time of writing, the following controllers have support: > > + > > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D > > +i2c-davinci Supports dynamic bus speed > > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D >=20 > This paragaph is easy to get outdated. We can document that only > controller drivers with the callback function implemented will work. > People then can find out if that applies for their driver... >=20 > There are some grammar correction in the Sashiko-review[1]. Most of them > look correct to me. Can you have a look at these, too, please? Sure, thanks for pointing that out. I will update the patch with the grammar corrections. >=20 > [1] https://sashiko.dev/#/patchset/20260324-i2c-mux-v9-0-5292b0608243%40g= mail.com Best regards, Marcus Folkesson