Re: [PATCH RESEND] drm/i915/display: Add quirk for interlane align bit on CH7511

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Fri, Jun 05, 2026 at 10:46:40AM +0200, Patrik Jakobsson wrote:
> When disabling pattern training after successful link training the
> CH7511 bridge incorrectly clears the INTERLANE_ALIGN_DONE bit. This is
> interpreted as link failure when rechecking the link status and triggers
> an endless loop of retraining sequences.
> 
> This patch adds a quirk to pretend the bit is still set and no
> retraining is needed.
> 
> Fixes: 3b3be899fc81 ("drm/i915/dp: Recheck link state after modeset")

Closes: ?

> Signed-off-by: Patrik Jakobsson <pjakobsson@suse.de>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c     |  9 +++++++++
>  drivers/gpu/drm/i915/display/intel_quirks.c | 17 +++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_quirks.h |  1 +
>  3 files changed, 27 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 85d3aa3b9894..5b269b1f18d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5875,6 +5875,15 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
>  	if (intel_dp->link.seq_train_failures)
>  		return true;
>  
> +	/*
> +	 * The CH7511 bridge incorrectly clears the INTERLANE_ALIGN_DONE bit
> +	 * when disabling training pattern.
> +	 */
> +	if (intel_has_dpcd_quirk(intel_dp, QUIRK_IGNORE_INTERLANE_ALIGN_BIT)) {
> +		link_status[DP_LANE_ALIGN_STATUS_UPDATED - DP_LANE0_1_STATUS] |=
> +			DP_INTERLANE_ALIGN_DONE;
> +	}
> +
>  	/* Retrain if link not ok */
>  	return !intel_dp_link_ok(intel_dp, link_status) &&
>  		!intel_psr_link_ok(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c
> index 33245f44c0d5..2cec0a945528 100644
> --- a/drivers/gpu/drm/i915/display/intel_quirks.c
> +++ b/drivers/gpu/drm/i915/display/intel_quirks.c
> @@ -100,6 +100,14 @@ static void quirk_disable_psr2(struct intel_display *display)
>  	drm_info(display->drm, "PSR2 support not currently available for this setup, applying disable PSR2 quirk\n");
>  }
>  
> +static void quirk_ignore_interlane_align_bit(struct intel_dp *intel_dp)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +
> +	intel_set_dpcd_quirk(intel_dp, QUIRK_IGNORE_INTERLANE_ALIGN_BIT);
> +	drm_info(display->drm, "Applying ignore interlane align bit quirk\n");
> +}
> +
>  struct intel_quirk {
>  	int device;
>  	int subsystem_vendor;
> @@ -286,6 +294,15 @@ static const struct intel_dpcd_quirk intel_dpcd_quirks[] = {
>  		.sink_oui = SINK_OUI(0x00, 0x22, 0xb9),
>  		.hook = quirk_disable_edp_panel_replay,
>  	},
> +	/* Nodka TPC6000-C152 */
> +	{
> +		.device = 0x0f31,
> +		.subsystem_vendor = 0x8086,
> +		.subsystem_device = 0x0f31,
> +		.sink_oui = SINK_OUI(0x2b, 0x02, 0xf0),
> +		.sink_device_id = SINK_DEVICE_ID('C', 'H', '7', '5', '1', '1'),
> +		.hook = quirk_ignore_interlane_align_bit,
> +	},
>  };
>  
>  void intel_init_quirks(struct intel_display *display)
> diff --git a/drivers/gpu/drm/i915/display/intel_quirks.h b/drivers/gpu/drm/i915/display/intel_quirks.h
> index 970a4fe52faf..7fcc3967f84f 100644
> --- a/drivers/gpu/drm/i915/display/intel_quirks.h
> +++ b/drivers/gpu/drm/i915/display/intel_quirks.h
> @@ -23,6 +23,7 @@ enum intel_quirk_id {
>  	QUIRK_EDP_LIMIT_RATE_HBR2,
>  	QUIRK_DISABLE_EDP_PANEL_REPLAY,
>  	QUIRK_DISABLE_PSR2,
> +	QUIRK_IGNORE_INTERLANE_ALIGN_BIT,
>  };
>  
>  void intel_init_quirks(struct intel_display *display);
> -- 
> 2.54.0

-- 
Ville Syrjälä
Intel