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[104.155.91.135]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-492203d2449sm238175265e9.14.2026.06.15.06.16.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2026 06:16:10 -0700 (PDT) Date: Mon, 15 Jun 2026 14:16:06 +0100 From: Vincent Donnefort To: tabba@google.com Cc: Marc Zyngier , Oliver Upton , Will Deacon , Catalin Marinas , Quentin Perret , Sebastian Ene , Per Larsen , Suzuki K Poulose , Zenghui Yu , Joey Gouly , Steffen Eiden , Mark Rutland , Jonathan Cameron , Hyunwoo Kim , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 06/11] KVM: arm64: Factor out reusable vCPU reset helpers Message-ID: References: <20260612065925.755562-1-tabba@google.com> <20260612065925.755562-7-tabba@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260612065925.755562-7-tabba@google.com> On Fri, Jun 12, 2026 at 07:59:20AM +0100, tabba@google.com wrote: > Pull the reusable pieces out of kvm_reset_vcpu(): expose the reset > PSTATE values in kvm_arm.h, and split the core register reset and the > PSCI-driven reset into kvm_reset_vcpu_core() and kvm_reset_vcpu_psci(). > A follow-up series reuses these to reset protected vCPUs at EL2. > > No functional change intended. > > Signed-off-by: Fuad Tabba > --- > arch/arm64/include/asm/kvm_arm.h | 12 ++++++ > arch/arm64/include/asm/kvm_emulate.h | 58 +++++++++++++++++++++++++++ > arch/arm64/kvm/reset.c | 60 ++-------------------------- > 3 files changed, 73 insertions(+), 57 deletions(-) > > diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h > index 3f9233b5a130..aba4ec09acd2 100644 > --- a/arch/arm64/include/asm/kvm_arm.h > +++ b/arch/arm64/include/asm/kvm_arm.h > @@ -348,4 +348,16 @@ > { PSR_AA32_MODE_UND, "32-bit UND" }, \ > { PSR_AA32_MODE_SYS, "32-bit SYS" } > > +/* > + * ARMv8 Reset Values > + */ > +#define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \ > + PSR_F_BIT | PSR_D_BIT) > + > +#define VCPU_RESET_PSTATE_EL2 (PSR_MODE_EL2h | PSR_A_BIT | PSR_I_BIT | \ > + PSR_F_BIT | PSR_D_BIT) > + > +#define VCPU_RESET_PSTATE_SVC (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \ > + PSR_AA32_I_BIT | PSR_AA32_F_BIT) > + > #endif /* __ARM64_KVM_ARM_H__ */ > diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h > index aed9fc0b717b..8436e71c402d 100644 > --- a/arch/arm64/include/asm/kvm_emulate.h > +++ b/arch/arm64/include/asm/kvm_emulate.h > @@ -704,4 +704,62 @@ static inline void vcpu_set_hcrx(struct kvm_vcpu *vcpu) > vcpu->arch.hcrx_el2 |= HCRX_EL2_EnASR; > } > } > + > +/* Reset a vcpu's core registers. */ > +static inline void kvm_reset_vcpu_core(struct kvm_vcpu *vcpu) > +{ > + u32 pstate; > + > + if (vcpu_el1_is_32bit(vcpu)) { > + pstate = VCPU_RESET_PSTATE_SVC; > + } else if (vcpu_has_nv(vcpu)) { > + pstate = VCPU_RESET_PSTATE_EL2; > + } else { > + pstate = VCPU_RESET_PSTATE_EL1; > + } nit: no brackes here, actually there were none before. > + > + /* Reset core registers */ > + memset(vcpu_gp_regs(vcpu), 0, sizeof(*vcpu_gp_regs(vcpu))); > + memset(&vcpu->arch.ctxt.fp_regs, 0, sizeof(vcpu->arch.ctxt.fp_regs)); > + vcpu->arch.ctxt.spsr_abt = 0; > + vcpu->arch.ctxt.spsr_und = 0; > + vcpu->arch.ctxt.spsr_irq = 0; > + vcpu->arch.ctxt.spsr_fiq = 0; > + vcpu_gp_regs(vcpu)->pstate = pstate; > +} > + > +/* PSCI reset handling for a vcpu. */ > +static inline void kvm_reset_vcpu_psci(struct kvm_vcpu *vcpu, > + struct vcpu_reset_state *reset_state) > +{ > + unsigned long target_pc = reset_state->pc; > + > + /* Gracefully handle Thumb2 entry point */ > + if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) { > + target_pc &= ~1UL; > + vcpu_set_thumb(vcpu); > + } > + > + /* Propagate caller endianness */ > + if (reset_state->be) > + kvm_vcpu_set_be(vcpu); > + > + *vcpu_pc(vcpu) = target_pc; > + > + /* > + * We may come from a state where either a PC update was > + * pending (SMC call resulting in PC being increpented to > + * skip the SMC) or a pending exception. Make sure we get > + * rid of all that, as this cannot be valid out of reset. > + * > + * Note that clearing the exception mask also clears PC > + * updates, but that's an implementation detail, and we > + * really want to make it explicit. > + */ > + vcpu_clear_flag(vcpu, PENDING_EXCEPTION); > + vcpu_clear_flag(vcpu, EXCEPT_MASK); > + vcpu_clear_flag(vcpu, INCREMENT_PC); > + vcpu_set_reg(vcpu, 0, reset_state->r0); > +} > + > #endif /* __ARM64_KVM_EMULATE_H__ */ > diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c > index 60969d90bdd3..e22d0be9e57c 100644 > --- a/arch/arm64/kvm/reset.c > +++ b/arch/arm64/kvm/reset.c > @@ -34,18 +34,6 @@ > static u32 __ro_after_init kvm_ipa_limit; > unsigned int __ro_after_init kvm_host_sve_max_vl; > > -/* > - * ARMv8 Reset Values > - */ > -#define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \ > - PSR_F_BIT | PSR_D_BIT) > - > -#define VCPU_RESET_PSTATE_EL2 (PSR_MODE_EL2h | PSR_A_BIT | PSR_I_BIT | \ > - PSR_F_BIT | PSR_D_BIT) > - > -#define VCPU_RESET_PSTATE_SVC (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \ > - PSR_AA32_I_BIT | PSR_AA32_F_BIT) > - > unsigned int __ro_after_init kvm_sve_max_vl; > > int __init kvm_arm_init_sve(void) > @@ -191,7 +179,6 @@ void kvm_reset_vcpu(struct kvm_vcpu *vcpu) > { > struct vcpu_reset_state reset_state; > bool loaded; > - u32 pstate; > > scoped_guard(spinlock, &vcpu->arch.mp_state_lock) { > reset_state = vcpu->arch.reset_state; > @@ -210,21 +197,8 @@ void kvm_reset_vcpu(struct kvm_vcpu *vcpu) > kvm_vcpu_reset_sve(vcpu); > } > > - if (vcpu_el1_is_32bit(vcpu)) > - pstate = VCPU_RESET_PSTATE_SVC; > - else if (vcpu_has_nv(vcpu)) > - pstate = VCPU_RESET_PSTATE_EL2; > - else > - pstate = VCPU_RESET_PSTATE_EL1; > - > /* Reset core registers */ > - memset(vcpu_gp_regs(vcpu), 0, sizeof(*vcpu_gp_regs(vcpu))); > - memset(&vcpu->arch.ctxt.fp_regs, 0, sizeof(vcpu->arch.ctxt.fp_regs)); > - vcpu->arch.ctxt.spsr_abt = 0; > - vcpu->arch.ctxt.spsr_und = 0; > - vcpu->arch.ctxt.spsr_irq = 0; > - vcpu->arch.ctxt.spsr_fiq = 0; > - vcpu_gp_regs(vcpu)->pstate = pstate; > + kvm_reset_vcpu_core(vcpu); > > /* Reset system registers */ > kvm_reset_sys_regs(vcpu); > @@ -233,36 +207,8 @@ void kvm_reset_vcpu(struct kvm_vcpu *vcpu) > * Additional reset state handling that PSCI may have imposed on us. > * Must be done after all the sys_reg reset. > */ > - if (reset_state.reset) { > - unsigned long target_pc = reset_state.pc; > - > - /* Gracefully handle Thumb2 entry point */ > - if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) { > - target_pc &= ~1UL; > - vcpu_set_thumb(vcpu); > - } > - > - /* Propagate caller endianness */ > - if (reset_state.be) > - kvm_vcpu_set_be(vcpu); > - > - *vcpu_pc(vcpu) = target_pc; > - > - /* > - * We may come from a state where either a PC update was > - * pending (SMC call resulting in PC being increpented to > - * skip the SMC) or a pending exception. Make sure we get > - * rid of all that, as this cannot be valid out of reset. > - * > - * Note that clearing the exception mask also clears PC > - * updates, but that's an implementation detail, and we > - * really want to make it explicit. > - */ > - vcpu_clear_flag(vcpu, PENDING_EXCEPTION); > - vcpu_clear_flag(vcpu, EXCEPT_MASK); > - vcpu_clear_flag(vcpu, INCREMENT_PC); > - vcpu_set_reg(vcpu, 0, reset_state.r0); > - } > + if (reset_state.reset) > + kvm_reset_vcpu_psci(vcpu, &reset_state); > > /* Reset timer */ > kvm_timer_vcpu_reset(vcpu); > -- > 2.54.0.1136.gdb2ca164c4-goog >