Re: [PATCH v4 0/2] x86/tsc: Exempt recent UV systems from clocksource watchdog checks to avoid false positives.

[Jiri Wiesner <jwiesner@suse.de>]

On Tue, Jun 09, 2026 at 02:34:10PM -0500, Dimitri Sivanich wrote:
> On Tue, Jun 09, 2026 at 11:59:26AM +0200, Jiri Wiesner wrote:
> > On Thu, May 21, 2026 at 09:08:34PM -0500, Dimitri Sivanich wrote:
> > > On Thu, May 21, 2026 at 09:30:14PM +0200, Thomas Gleixner wrote:
> > > > On Thu, May 21 2026 at 08:17, Dimitri Sivanich wrote:
> > > > > HPE UV hardware and firmware is designed to ensure a reliable and
> > > > > synchronized TSC mechanism.  Comparing the TSC against secondary
> > > > > clocksources can result in false positives due to variable access
> > > > > latency caused by system traffic.
> > 
> > I do not think that the access latency of the reference clocksource, sgi_rtc in this case, is the cause of the false positives. I think sgi_rtc really experiences time skew. More details below.
> 
> FYI, there was a firmware regression that impacted sgi_rtc on our Sapphire
> Rapids based UV systems, that would've caused the results that you saw.
> That has since been fixed.

It may not seem so but I was actually trying to help make the argument for why this little patchset disabling the clocksource watchdog on UV systems should be merged. I think still think the view that the false positives are caused by the access latency of sgi_rtc contradicts the way the new clocksource watchdog implementation works. Details are below.

> > > I tested a 7.1-rc4 kernel on a 2048 thread 16 socket system and, while
> > > under test, the TSC did get marked as unstable after a series of "sgi_rtc
> > > read timed out" warnings.
> > 
> > The new clocksource watchdog implementation makes sure to act on time skew only if the time between two reference clocksource readouts does not exceed 50 us. The threshold for evaluating time skew (based on SHIFT_500PPM) is 244 us for a 500 ms interval plus the measured reference clocksource readout latency. If the comparison to the reference clocksource fails on CPU 0 the time skew between the clocksource being checked and the reference clocksource must be at least 244 us. The clocksource watchdog cannot distiguish which of the clocksources is skewed, and it must make the assumption that the clocksource being checked is skewed.

The code executes:
scoped_guard(irq) {
	wd_ts0 = watchdog->read(watchdog);
	cs_ts = cs->read(cs);
	wd_ts1 = watchdog->read(watchdog);
}
which I imagine works in this way:

* send a request to sgi_rtc
* read sgi_rtc timestamp (wd_ts0)
* return timestamp from sgi_rtc
* read TSC timestamp on the CPU
* send a request to sgi_rtc
* read sgi_rtc timestamp (wd_ts1)
* return timestamp from sgi_rtc

The code calculates wd_seq by subtracting wd_ts0 from wd_ts1. wd_seq includes the time needed to (assuming the sgi_rtc timestamp read takes zero time):
* return timestamp from sgi_rtc
* read TSC timestamp on the CPU
* send a request to sgi_rtc
The code guarantees that wd_seq is less than 50 us, which means the latency between reading wd_ts0 and reading cs_ts must also be less than 50 us. In other words, when a clocksource fails to pass the frequency check there is provable time skew. Either the TSC got skewed, which produced most of the measured time skew, or sgi_rtc got skewed (maybe both got skewed to a considerable degree but that seems is unlikely). The case described below provides an example of an sgi_rtc clocksource experiencing time skew. If the below example was caused by a firmware bug that has since been resolved, there needs to be another bug causing the time skew of sgi_rtc, based on the reported false positive of the new clocksource watchdog implementation on a UV system. Otherwise, we will have to blame the TSC and the clocksource watchdog should not be disabled on UV systems.

> > In the past, I worked on a bug where a customer with an HPE UV machine reported degraded performance and switches to the HPET. This kernel had the old clocksource watchdog implementation. I created a debugging kernel with the HPET as a second watchdog (not affecting the decisions by the watchdog) and got this result:
> > > clocksource: timekeeping watchdog on CPU118: Marking clocksource 'tsc' as unstable because the skew is too large:
> > > clocksource: 'sgi_rtc' wd_nsec: 511302794 wd_now: 1cb50e4c4b wd_last: 1ca7097111 mask: ffffffffffffff
> > > clocksource: 'hpet' wd2_nsec: 512005960 wd2_now: 65892719 wd2_last: 64c5d684 mask: ffffffff
> > > clocksource: 'tsc' cs_nsec: 512006458 cs_now: 86b5982cb1 cs_last: 867581bbab mask: ffffffffffffffff
> > > clocksource: 'tsc' skewed 703664 ns (0 ms) over watchdog 'sgi_rtc' interval of 511302794 ns (511 ms)
> > > clocksource: 'tsc' is current clocksource.
> > > tsc: Marking TSC unstable due to clocksource watchdog
> > > clocksource: Checking clocksource tsc synchronization from CPU 610 to CPUs 0-609,611-767.
> > > clocksource: Switched to clocksource sgi_rtc

The machine has 8 CPU sockets with Intel(R) Xeon(R) Platinum 8468H (family: 0x6, model: 0x8f, stepping: 0x8), cpu ucode 0x2b000620:
[    0.000000] DMI: HPE Compute Scale-up Server 3200/Compute Scale-up Server 3200, BIOS Bundle:1.60.88-20250613_054523 SFW:009.040.012.000.25060304
[    0.675393] UV: Found UV500 hub
[    0.679294] UV: UVsystab: Revision:500
The test was carried out on 22nd May, 2025.

> > The intervals measured by the TSC and the HPET match very well; the sgi_rtc is off. I find it hard to believe that both the TSC and the HPET would be skewed - both reporting a longer interval - while sgi_rtc was correct. I think sgi_rtc was skewed.
> > 
> > There are several solution to work around the hardware limitation of sgi_rtc:
> > 1. Disable the clocksource watchdog
> > 2. Decrease the rating of sgi_rtc

Solution 1 is actionable but I think we should be sure it is made for the right reasons.
-- 
Jiri Wiesner
SUSE Labs