From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
To: Biju <biju.das.au@gmail.com>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>,
dri-devel@lists.freedesktop.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 07/16] dt-bindings: display: renesas,rzg2l-du: Document RZ/G3L SoC
Date: Wed, 8 Jul 2026 18:45:40 +0200 [thread overview]
Message-ID: <ak5-tIYnLmHps4M4@tom-desktop> (raw)
In-Reply-To: <20260704093433.273672-8-biju.das.jz@bp.renesas.com>
Hi Biju,
Thanks for your patch.
On Sat, Jul 04, 2026 at 10:34:17AM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> The DU block on the RZ/G3L SoC is identical to the one found on the RZ/G2L
> SoC. However, it supports the DSI, DPI, and LVDS interfaces, while the
> RZ/G2L supports only the DSI and DPI interfaces.
>
> Due to this difference, a SoC-specific compatible string,
> 'renesas,r9a08g046-du', is added for the RZ/G3L SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> .../bindings/display/renesas,rzg2l-du.yaml | 27 +++++++++++++++++--
> 1 file changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> index 7c84a9ecc7a7..65368649fe77 100644
> --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> @@ -20,6 +20,7 @@ properties:
> - enum:
> - renesas,r9a07g043u-du # RZ/G2UL
> - renesas,r9a07g044-du # RZ/G2{L,LC}
> + - renesas,r9a08g046-du # RZ/G3L
> - renesas,r9a09g057-du # RZ/V2H(P)
> - renesas,r9a09g077-du # RZ/T2H
> - items:
> @@ -65,7 +66,7 @@ properties:
> model-dependent. Each port shall have a single endpoint.
>
> patternProperties:
> - "^port@[0-1]$":
> + "^port@[0-2]$":
> $ref: /schemas/graph.yaml#/properties/port
> unevaluatedProperties: false
>
> @@ -88,7 +89,6 @@ required:
> - clocks
> - clock-names
> - power-domains
> - - ports
> - renesas,vsps
>
> additionalProperties: false
> @@ -108,6 +108,7 @@ allOf:
> port@0:
> description: DPI
> port@1: false
> + port@2: false
>
> required:
> - port@0
> @@ -124,10 +125,31 @@ allOf:
> description: DSI
> port@1:
> description: DPI
> + port@2: false
>
> required:
> - port@0
> - port@1
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a08g046-du
> + then:
> + properties:
> + port:
> + properties:
> + endpoint@0:
> + description: DSI
> + endpoint@1:
> + description: DPI
> + endpoint@2:
> + description: LVDS
I'm seeing you are using ports + port@{0,1,2} in driver and soc .dtsi
so I think here we will need to have ports + port@{0,1,2} aswell.
Kind Regards,
Tommaso
> +
> + required:
> + - port@0
> + - port@1
> + - port@2
> - if:
> properties:
> compatible:
> @@ -140,6 +162,7 @@ allOf:
> port@0:
> description: DSI
> port@1: false
> + port@2: false
>
> required:
> - port@0
> --
> 2.43.0
>
next prev parent reply other threads:[~2026-07-08 16:46 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-04 9:34 [PATCH 00/16] Add support for DU, LVDS and DSI on the Renesas RZ/G3L SoC Biju
2026-07-04 9:34 ` [PATCH 01/16] dt-bindings: display: bridge: renesas,dsi: Document RZ/G3L Biju
2026-07-08 8:29 ` Krzysztof Kozlowski
2026-07-08 9:39 ` Biju Das
2026-07-04 9:34 ` [PATCH 02/16] drm: renesas: rzg2l_mipi_dsi: Add dphyctrl0_init_val to hw_info Biju
2026-07-04 9:34 ` [PATCH 03/16] drm: renesas: rzg2l_mipi_dsi: Add activation_dly " Biju
2026-07-04 9:34 ` [PATCH 04/16] drm: renesas: rzg2l_mipi_dsi: Move global timings into hardware info struct Biju
2026-07-04 9:34 ` [PATCH 05/16] drm: renesas: rzg2l_mipi_dsi: Add support for DSI PWRRDY Biju
2026-07-04 9:34 ` [PATCH 06/16] drm: renesas: rzg2l_mipi_dsi: Add RZ/G3L MIPI DSI support Biju
2026-07-04 9:34 ` [PATCH 07/16] dt-bindings: display: renesas,rzg2l-du: Document RZ/G3L SoC Biju
2026-07-08 8:30 ` Krzysztof Kozlowski
2026-07-08 8:38 ` Biju Das
2026-07-08 16:45 ` Tommaso Merciai [this message]
2026-07-08 17:12 ` Biju Das
2026-07-04 9:34 ` [PATCH 08/16] drm: renesas: rz-du: Add RZ/G3L (R9A08G046) DU support Biju
2026-07-08 17:01 ` Tommaso Merciai
2026-07-08 17:16 ` Biju Das
2026-07-04 9:34 ` [PATCH 09/16] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder Biju
2026-07-04 9:34 ` [PATCH 10/16] drm: renesas: rz-du: Add support for " Biju
2026-07-04 9:34 ` [PATCH 11/16] arm64: dts: renesas: r9a08g046: Add fcpvd node Biju
2026-07-04 9:34 ` [PATCH 12/16] arm64: dts: renesas: r9a08g046: Add vspd node Biju
2026-07-04 9:34 ` [PATCH 13/16] arm64: dts: renesas: r9a08g046: Add DU and DSI nodes Biju
2026-07-04 9:34 ` [PATCH 14/16] arm64: dts: renesas: r9a08g046: Add LVDS node Biju
2026-07-04 9:34 ` [PATCH 15/16] arm64: dts: renesas: Add DSI overlay for RZ/G3L SMARC EVK with ADV7535 Biju
2026-07-04 9:34 ` [PATCH 16/16] arm64: dts: renesas: Add LVDS overlay for RZ/G3L SMARC EVK with ITE6263 Biju
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