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[93.144.65.248]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-493b8c238fasm2254645e9.0.2026.06.29.09.40.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 09:40:31 -0700 (PDT) Date: Mon, 29 Jun 2026 18:40:29 +0200 From: Stefano Radaelli To: Frank Li Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, pierluigi.p@variscite.com, Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Subject: Re: [PATCH v5 06/14] arm64: dts: imx8mp-var-som-symphony: enable PCIe Message-ID: References: <26b5b602c3995a5a74f64b84576ab4d54ace23ee.1780929317.git.stefano.r@variscite.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Hi Frank, On Mon, Jun 29, 2026 at 12:30:09PM -0400, Frank Li wrote: > > You have to provide all clocks, otherwise, whole clocks and clock-names will > by overwrite with one clock "ref". > > suppose CHECK_DTBS should report warning about clocks items. > > Frank > thanks for checking. In this case the SoC dtsi does not provide any clocks or clock-names for the PCIe PHY node, so this is not overriding an existing clock list. It only adds the external reference clock used by the board. This follows the same pattern used by the i.MX8MP EVK, where the PCIe PHY node only provides the external "ref" clock together with fsl,refclk-pad-mode = . This is also why CHECK_DTBS does not report any warnings for this node. $: sed -n '/^&pcie_phy {/,/^};/p' arch/arm64/boot/dts/freescale/imx8mp-evk.dts &pcie_phy { fsl,refclk-pad-mode = ; clocks = <&pcie0_refclk>; clock-names = "ref"; status = "okay"; }; Thanks, Stefano