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Mon, 29 Jun 2026 21:14:50 -0700 Date: Mon, 29 Jun 2026 21:14:48 -0700 From: Nicolin Chen To: Pranjal Shrivastava CC: , , , , , , , , , , , , , Subject: Re: [PATCH rc v6 3/7] iommu/arm-smmu-v3: Do not enable EVTQ/PRIQ interrupts in kdump kernel Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D2:EE_|MW6PR12MB7086:EE_ X-MS-Office365-Filtering-Correlation-Id: f2b89b1d-f5d1-4e29-5493-08ded65e2ba7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|36860700016|376014|1800799024|23010399003|18002099003|22082099003|11063799006|56012099006|4143699003|6133799003; X-Microsoft-Antispam-Message-Info: jcAQYOH/OPHVlgFjA+gBMyJyHDsvmzxOshOXa29tF0tKBSphgsCC9yUPx0l0rgBj+y9a9O2Gz5wkWNu8vXI3hCf91md3OYTyHA5ghMHNy0P5UaqWymKbgah0yLNdv7789+/awrche2BXhBqiFHhcRIWSOY073hoct/C4C/4Al93jiFHMfsuHNqg61+7vUT1aPIP0jZVm7yPVrvtKNMUbHyoRzzqX6BfJFwrEgLD3qb30ftIW9bMblxVxwXs3Dqc2rfuZ3h7SYyEqJZVxzd0vGVZNCJB0ix+z0/OaD9IsoGoAqzEG1pDG9xgrKSHglT/XkLhmq6vwRcNvik3VC8Z4bMzeBZ2unC75NlWkJsjQv/f6nv3OhHhDPStcwH/KW6RZAunujORWKWS00cxbc6nmEeHFQ/gfNPk7RY20BeCuGkt7zhWXDgvPk34bjCEMIDbPtnWzwdAh6Vaeaucx899ZSm9qcgNYU91r2f3BSUFf50SnaS17mfzKBNeo0X7ctc5QVEDScP4i8sQWhQNZ9t+iLlNnbm1YkW/tFTYNYryYnNy5X8FVjPO0bw+oF5+KGmeec2gX1Xi2uQVLy7fGy5Alp8SebhkJn1yl9+2TgLpGyFBN+X2GNTz12iHj4YXp+A6gN/lNdKSxuOBgQIp7Hf5DRyxGNkHJCHlejrMOdR4TtLmDAg7feQaIAL5hEgW44Rl/8Nn6c+U91eBjdEIwYKG3TQ== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(36860700016)(376014)(1800799024)(23010399003)(18002099003)(22082099003)(11063799006)(56012099006)(4143699003)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: yXClJeW0YU10mFQY/bxvcoWPe5zau4m8Zf16a1MwvdM96HfPoZgOo2SwPc3inBZ4pZEjnABgl/jy6/gEajjAtjB3MnARzc3VMwuskgz2IsM42X/DmjNNnXP6iDQy0OBqIG5DYKKZGLFtnt7b8qppqN5BjXv2z6n0Cix6tV35xxhWptkOsvhk+B9UshG+mdj3Ll/ENQX79QSlA9UeM2M+sT3e32CizsMxecFG+0+zResugiMKJ9bjSj/UTgytbsrJCdWEgBqdEH89qSggXull4ylteXwFofakW0q29WtvdoHni7Gok6pwrHVkioRpG5GjCjRo0OIjinCJ95PB4GkOdjZZSuaq+5y9Qnh96LIKX3sgreXJZAJVAdCyja7+Hs88Jacxg+Kx3P3cSbehtMnmk8YecBQH6hJcVcPE4/wbIIanWCFm14aIAlcxXJRbPsmk X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2026 04:15:07.8571 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2b89b1d-f5d1-4e29-5493-08ded65e2ba7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB7086 On Mon, Jun 29, 2026 at 08:48:11AM +0000, Pranjal Shrivastava wrote: > On Wed, May 20, 2026 at 10:03:20AM -0700, Nicolin Chen wrote: > > @@ -5020,19 +5029,30 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) > > /* > > * Cavium ThunderX2 implementation doesn't support unique irq > > * lines. Use a single irq line for all the SMMUv3 interrupts. > > + * > > + * In kdump, EVTQ/PRIQ are disabled, so no threaded handling. > > */ > > - ret = devm_request_threaded_irq(smmu->dev, irq, > > - arm_smmu_combined_irq_handler, > > - arm_smmu_combined_irq_thread, > > - IRQF_ONESHOT, > > - "arm-smmu-v3-combined-irq", smmu); > > + if (is_kdump_kernel()) > > + ret = devm_request_irq(smmu->dev, irq, > > + arm_smmu_combined_irq_handler, 0, > > + "arm-smmu-v3-combined-irq", > > + smmu); > > This `if` isn't needed, we can continue using devm_request_threaded_irq, > if you look at the doc for devm_request_threaded_irq [1] it says: [...] > So, we can pass handler() here while leaving the thread_fn == NULL: > > ret = devm_request_threaded_irq(smmu->dev, irq, > arm_smmu_combined_irq_handler, > is_kdump_kernel() ? NULL : arm_smmu_combined_irq_thread, > IRQF_ONESHOT, > "arm-smmu-v3-combined-irq", smmu); Are you sure? __setup_irq(): 1497- /* 1498: * IRQF_ONESHOT means the interrupt source in the IRQ chip will be 1499- * masked until the threaded handled is done. If there is no thread 1500: * handler then it makes no sense to have IRQF_ONESHOT. 1501- */ 1502: WARN_ON_ONCE(new->flags & IRQF_ONESHOT && !new->thread_fn); > Additionally, the arm_smmu_combined_irq_handler() returns > IRQ_WAKE_THREAD unconditionally, which causes us to hit the warn_on[3] in > __handle_irq_event_percpu. arm_smmu_combined_irq_handler() does not return IRQ_WAKE_THREAD unconditionally. This is the first part of PATCH-3 in v6: @@ -2464,7 +2464,11 @@ static irqreturn_t arm_smmu_combined_irq_thread(int irq, void *dev) static irqreturn_t arm_smmu_combined_irq_handler(int irq, void *dev) { - arm_smmu_gerror_handler(irq, dev); + irqreturn_t ret = arm_smmu_gerror_handler(irq, dev); + + /* In kdump, EVTQ/PRIQ are disabled and there is no thread to wake */ + if (is_kdump_kernel()) + return ret; return IRQ_WAKE_THREAD; } Nicolin