From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-dy1-f178.google.com (mail-dy1-f178.google.com [74.125.82.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D55B37AA81 for ; Tue, 30 Jun 2026 06:14:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.82.178 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782800055; cv=none; b=tKZmNdqxBGQDjUU2Cs9w4AGaIKrl04hJJFXMjIvLADEOw+Hvfu3KY4XGNZVdacAJv3QkdzDYZZpDCDz0puy5rsLRtCjBC178REJ4BTuY0oo0RKjqbgGSHDQ+ZfF6h/+aAdzSxRweJ5DtqH1D6bATNsPnlTvF4iZVO46ss1qWNhE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782800055; c=relaxed/simple; bh=BCX2akkhmmnaIZWDdudQQH9BULKqJHzDvO2oUnBo4gM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ryOsW+KyEWXiF4rjZmrRG1VbIB+9r4jqKwFQ49HPGA3g5A+3v2xeBkiVa/jFyRjC9BXxj2X6n2f8RsipK0/HPmB2H6fy+N89/JO6D1DnWrPmq9PrafD5HTaZHTGVFETmwSBFzOSMW7dNWDsuz6nCB/DII5lcAKEXebM6RSlzbOY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=W/VvzIea; arc=none smtp.client-ip=74.125.82.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="W/VvzIea" Received: by mail-dy1-f178.google.com with SMTP id 5a478bee46e88-30df5854e1eso252927eec.0 for ; Mon, 29 Jun 2026 23:14:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1782800053; x=1783404853; darn=vger.kernel.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=kQ4pwxtyxCm1G5M66xxdmEUDpbEAdNwzhoPavDK6tNs=; b=W/VvzIeaDL5z/x4oWJH9DmLoCBvoKVdXFEo54vs7MKd7DG4eVXfaYAviGkbLa1Uf1k LJ/XaPkIw/5Zke3cW2L9EqRWOMsIbbMMEt3GHXA04jp4s4Gt2CmguXuMIybMyrC1GXkL /R88k2NYAPsdPMKmBNZOBZjuGCaqIiFtJbLFKJsXeNMF4g34w7eO2zvI4z5itZNY1kCJ SvxprX9Uq2jIvIUQk7bmJ4sb2TIAZH237u0cCzy2BkpomGKc0p0MLwUQuYDtLk5YMw6m Tc5Svu27E6abYzzAzlW0c2mKxnlwhgiDDOwcyuhd3gOR1rZ2xCV1paDVihKer6BCOTag eZlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782800053; x=1783404853; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=kQ4pwxtyxCm1G5M66xxdmEUDpbEAdNwzhoPavDK6tNs=; b=AbDh1ImiCNINYkWkV2sW3s0PdFbEMZTa4YxvMVVwHP7i+PQMQnxEqx59QxF52PqvJp CHdZEVURWx6hSeI1MvC7gt4HJHMPQqG1IUmX5PgvtutOiBIeFGw3zK5S/SXJwvOz4qJL SU6IIsKEe+yHVlt/Ixx6302uozhJLYIuIcOJHUMDxyiJP/nVW/rdTIB2wPEP4irWBYb+ 9/goLLCTmXLUWQ/p8KkzYOcbN0AtE4aFO8dDidVrtSYvVqTulqk7pQs/IYRO5+IvmIou kPU4goubXMZAZ/DQ9IGQeNdOBPoT14fEq53zwC9yzF9uwa6bm35HXGD2usT+iXNtEyI2 p5hg== X-Forwarded-Encrypted: i=1; AHgh+RrDbnioV6f7VZKBPGke5C5NbgsS15e6O+CMwwevdremxVI9sQWoxz+rFf4OivTwePju+ViGj7E82gkPtx0=@vger.kernel.org X-Gm-Message-State: AOJu0YxGQo/+KDfFWxxJyk0QocS3mrnt4BcQAOmhIjcD5oHRnwx28ltO cknZRlg9uG1N/G3jPJmJ9WT1caSA3Lt7izS4i2YlutfVpG6XFm0YM6LC X-Gm-Gg: AfdE7cl24Y98QE1+I6ebriDMEkI7+er5ypThYEhk+mwnY37rdNHDT8gBiaQP6jhD+tA h1IYNB8ABf1dtA4lLkaLmobzpvCzfUjqtnQo2VVr10xtBrVoMcylLz9LQscmFmepuNoEVwj1xJA UOKcg4lXg7LYEPbsZ+bNepCkPjZz4i1HMkwbexS6PKc7B19+aSzqdcUubivzHWclPjmf7rRrYW5 nSoauaQTT//4bhqKi/PWVk8xoF60gd0HCidBbImny5qg5oGAei8xeWIXOQrX+ynSKhcDhOuCfNa 1s9B3SWJJKdh1aGIRFbdh/1E18pSbexdVl1DOwUT2X0PjwUWI6Ahszqz1UGxW5P3woqj7RFjcFx zaSyXVcWheaFF5GTT0fBf1S2/o/3sJ0gQP4hV1TkluNPdcBrvrvDr4k0URmRhqMhvK7RkykVXUb vxeksdtjTqrfZrdZcslG5T92h9evKJAzS0 X-Received: by 2002:a05:7300:6115:b0:30c:9ca4:5cd0 with SMTP id 5a478bee46e88-30ee9f63cdamr444602eec.4.1782800052515; Mon, 29 Jun 2026 23:14:12 -0700 (PDT) Received: from blinky ([2601:647:6700:64d0::94ac]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30ee326c7a7sm4344373eec.29.2026.06.29.23.14.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 23:14:11 -0700 (PDT) Date: Mon, 29 Jun 2026 23:14:09 -0700 From: Charlie Jenkins To: Jesse T Cc: Paul Walmsley , Palmer Dabbelt , Nam Cao , Alexandre Ghiti , Anup Patel , Atish Patra , Conor Dooley , Paolo Bonzini , Andrew Morton , Shuah Khan , Radim =?utf-8?B?S3LEjW3DocWZ?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v2 07/16] riscv: Use generated instruction headers for misaligned loads/stores Message-ID: References: <20260621-riscv_insn_table-v2-0-7f0810ee2274@gmail.com> <20260621-riscv_insn_table-v2-7-7f0810ee2274@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Mon, Jun 29, 2026 at 04:20:15PM -0400, Jesse T wrote: > On Mon, Jun 22, 2026 at 12:08 AM Charlie Jenkins via B4 Relay > wrote: > > > > From: Charlie Jenkins > > > > Migrate the misaligned loads/store code to use the generated instruction > > headers instead of the hand-written instruction composition functions. > > > > Signed-off-by: Charlie Jenkins > > > > --- > > > > Similar to the other patches of this series, I extracted out the logic > > of this function and brute forced all possible inputs to validate that > > the outputs are the same. To verify this change in the kernel, I booted > > on Spike and used the misaligned access checker which does some > > misaligned accesses. > > --- > > arch/riscv/kernel/traps_misaligned.c | 183 ++++++++++++++++------------------- > > 1 file changed, 83 insertions(+), 100 deletions(-) > > > > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c > > index 81b7682e6c6d..4d2a2432e0c4 100644 > > --- a/arch/riscv/kernel/traps_misaligned.c > > +++ b/arch/riscv/kernel/traps_misaligned.c > > @@ -22,15 +22,11 @@ > > > > #ifdef CONFIG_FPU > > > > -#define FP_GET_RD(insn) (insn >> 7 & 0x1F) > > - > > extern void put_f32_reg(unsigned long fp_reg, unsigned long value); > > > > -static int set_f32_rd(unsigned long insn, struct pt_regs *regs, > > +static int set_f32_rd(unsigned long fp_reg, struct pt_regs *regs, > > unsigned long val) > > { > > - unsigned long fp_reg = FP_GET_RD(insn); > > - > > put_f32_reg(fp_reg, val); > > regs->status |= SR_FS_DIRTY; > > > > @@ -39,9 +35,8 @@ static int set_f32_rd(unsigned long insn, struct pt_regs *regs, > > > > extern void put_f64_reg(unsigned long fp_reg, unsigned long value); > > > > -static int set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val) > > +static int set_f64_rd(unsigned long fp_reg, struct pt_regs *regs, u64 val) > > { > > - unsigned long fp_reg = FP_GET_RD(insn); > > unsigned long value; > > > > #if __riscv_xlen == 32 > > @@ -58,10 +53,8 @@ static int set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val) > > #if __riscv_xlen == 32 > > extern void get_f64_reg(unsigned long fp_reg, u64 *value); > > > > -static u64 get_f64_rs(unsigned long insn, u8 fp_reg_offset, > > - struct pt_regs *regs) > > +static u64 get_f64_rs(unsigned long fp_reg, struct pt_regs *regs) > > { > > - unsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F; > > u64 val; > > > > get_f64_reg(fp_reg, &val); > > @@ -73,10 +66,8 @@ static u64 get_f64_rs(unsigned long insn, u8 fp_reg_offset, > > > > extern unsigned long get_f64_reg(unsigned long fp_reg); > > > > -static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset, > > - struct pt_regs *regs) > > +static unsigned long get_f64_rs(unsigned long fp_reg, struct pt_regs *regs) > > { > > - unsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F; > > unsigned long val; > > > > val = get_f64_reg(fp_reg); > > @@ -89,10 +80,8 @@ static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset, > > > > extern unsigned long get_f32_reg(unsigned long fp_reg); > > > > -static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset, > > - struct pt_regs *regs) > > +static unsigned long get_f32_rs(unsigned long fp_reg, struct pt_regs *regs) > > { > > - unsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F; > > unsigned long val; > > > > val = get_f32_reg(fp_reg); > > @@ -107,28 +96,18 @@ static void set_f32_rd(unsigned long insn, struct pt_regs *regs, > > > > static void set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val) {} > > > > -static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset, > > - struct pt_regs *regs) > > +static unsigned long get_f64_rs(unsigned long fp_reg, struct pt_regs *regs) > > { > > return 0; > > } > > > > -static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset, > > - struct pt_regs *regs) > > +static unsigned long get_f32_rs(unsigned long fp_reg, struct pt_regs *regs) > > { > > return 0; > > } > > > > #endif > > > > -#define GET_F64_RS2(insn, regs) (get_f64_rs(insn, 20, regs)) > > -#define GET_F64_RS2C(insn, regs) (get_f64_rs(insn, 2, regs)) > > -#define GET_F64_RS2S(insn, regs) (get_f64_rs(RVC_RS2S(insn), 0, regs)) > > - > > -#define GET_F32_RS2(insn, regs) (get_f32_rs(insn, 20, regs)) > > -#define GET_F32_RS2C(insn, regs) (get_f32_rs(insn, 2, regs)) > > -#define GET_F32_RS2S(insn, regs) (get_f32_rs(RVC_RS2S(insn), 0, regs)) > > - > > #define __read_insn(regs, insn, insn_addr, type) \ > > ({ \ > > int __ret; \ > > @@ -217,13 +196,13 @@ static int handle_vector_misaligned_load(struct pt_regs *regs) > > } > > #endif > > > > -static int handle_scalar_misaligned_load(struct pt_regs *regs) > > +static noinline int handle_scalar_misaligned_load(struct pt_regs *regs) > > { > > union reg_data val; > > unsigned long epc = regs->epc; > > unsigned long insn; > > unsigned long addr = regs->badaddr; > > - int fp = 0, shift = 0, len = 0; > > + int fp = 0, shift = 0, len = 0, rd = 0; > > > > perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); > > > > @@ -240,68 +219,71 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) > > > > regs->epc = 0; > > > > - if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) { > > + if (riscv_insn_is_lw(insn)) { > > len = 4; > > shift = 8 * (sizeof(unsigned long) - len); > > -#if defined(CONFIG_64BIT) > > - } else if ((insn & INSN_MASK_LD) == INSN_MATCH_LD) { > > + rd = riscv_insn_lw_extract_xd(insn); > > + } else if (riscv_insn_is_ld(insn)) { > > len = 8; > > shift = 8 * (sizeof(unsigned long) - len); > > - } else if ((insn & INSN_MASK_LWU) == INSN_MATCH_LWU) { > > + rd = riscv_insn_ld_extract_xd(insn); > > + } else if (riscv_insn_is_lwu(insn)) { > > len = 4; > > -#endif > > - } else if ((insn & INSN_MASK_FLD) == INSN_MATCH_FLD) { > > + rd = riscv_insn_lwu_extract_xd(insn); > > + } else if (riscv_insn_is_fld(insn)) { > > fp = 1; > > len = 8; > > - } else if ((insn & INSN_MASK_FLW) == INSN_MATCH_FLW) { > > + rd = riscv_insn_fld_extract_fd(insn); > > + } else if (riscv_insn_is_flw(insn)) { > > fp = 1; > > len = 4; > > - } else if ((insn & INSN_MASK_LH) == INSN_MATCH_LH) { > > + rd = riscv_insn_flw_extract_fd(insn); > > + } else if (riscv_insn_is_lh(insn)) { > > len = 2; > > shift = 8 * (sizeof(unsigned long) - len); > > - } else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) { > > + rd = riscv_insn_lh_extract_xd(insn); > > + } else if (riscv_insn_is_lhu(insn)) { > > len = 2; > > -#if defined(CONFIG_64BIT) > > - } else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) { > > + rd = riscv_insn_lhu_extract_xd(insn); > > + } else if (riscv_insn_is_c_ld(insn)) { > > len = 8; > > shift = 8 * (sizeof(unsigned long) - len); > > - insn = RVC_RS2S(insn) << SH_RD; > > - } else if ((insn & INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP && > > - ((insn >> SH_RD) & 0x1f)) { > > + rd = (8 + riscv_insn_c_ld_extract_xd(insn)); > > + } else if (riscv_insn_is_c_ldsp(insn)) { > > len = 8; > > shift = 8 * (sizeof(unsigned long) - len); > > -#endif > > - } else if ((insn & INSN_MASK_C_LW) == INSN_MATCH_C_LW) { > > + rd = riscv_insn_c_ldsp_extract_xd(insn); > > + } else if (riscv_insn_is_c_lw(insn)) { > > len = 4; > > shift = 8 * (sizeof(unsigned long) - len); > > - insn = RVC_RS2S(insn) << SH_RD; > > - } else if ((insn & INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP && > > - ((insn >> SH_RD) & 0x1f)) { > > + rd = (8 + riscv_insn_c_lw_extract_xd(insn)); > > + } else if (riscv_insn_is_c_lwsp(insn)) { > > len = 4; > > shift = 8 * (sizeof(unsigned long) - len); > > - } else if ((insn & INSN_MASK_C_FLD) == INSN_MATCH_C_FLD) { > > + rd = riscv_insn_c_lwsp_extract_xd(insn); > > + } else if (riscv_insn_is_c_fld(insn)) { > > fp = 1; > > len = 8; > > - insn = RVC_RS2S(insn) << SH_RD; > > - } else if ((insn & INSN_MASK_C_FLDSP) == INSN_MATCH_C_FLDSP) { > > + rd = (8 + riscv_insn_c_fld_extract_fd(insn)); > > + } else if (riscv_insn_is_c_fldsp(insn)) { > > fp = 1; > > len = 8; > > -#if defined(CONFIG_32BIT) > > - } else if ((insn & INSN_MASK_C_FLW) == INSN_MATCH_C_FLW) { > > + rd = riscv_insn_c_fldsp_extract_fd(insn); > > + } else if (riscv_insn_is_c_flw(insn)) { > > fp = 1; > > len = 4; > > - insn = RVC_RS2S(insn) << SH_RD; > > - } else if ((insn & INSN_MASK_C_FLWSP) == INSN_MATCH_C_FLWSP) { > > + rd = (8 + riscv_insn_c_flw_extract_fd(insn)); > > + } else if (riscv_insn_is_c_flwsp(insn)) { > > fp = 1; > > len = 4; > > -#endif > > - } else if ((insn & INSN_MASK_C_LHU) == INSN_MATCH_C_LHU) { > > + rd = riscv_insn_c_flwsp_extract_fd(insn); > > + } else if (riscv_insn_is_c_lhu(insn)) { > > len = 2; > > - insn = RVC_RS2S(insn) << SH_RD; > > - } else if ((insn & INSN_MASK_C_LH) == INSN_MATCH_C_LH) { > > + rd = (8 + riscv_insn_c_lhu_extract_xd(insn)); > > + } else if (riscv_insn_is_c_lh(insn)) { > > len = 2; > > - shift = 8 * (sizeof(ulong) - len); > > - insn = RVC_RS2S(insn) << SH_RD; > > + shift = 8 * (sizeof(unsigned long) - len); > > + rd = (8 + riscv_insn_c_lh_extract_xd(insn)); > > } else { > > regs->epc = epc; > > return -1; > > @@ -319,11 +301,11 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) > > } > > > > if (!fp) > > - SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift); > > + *(unsigned long *)((unsigned long *)regs + rd) = val.data_ulong << shift; > > else if (len == 8) > > - set_f64_rd(insn, regs, val.data_u64); > > + set_f64_rd(rd, regs, val.data_u64); > > else > > - set_f32_rd(insn, regs, val.data_ulong); > > + set_f32_rd(rd, regs, val.data_ulong); > > > > regs->epc = epc + INSN_LEN(insn); > > > > @@ -336,7 +318,7 @@ static int handle_scalar_misaligned_store(struct pt_regs *regs) > > unsigned long epc = regs->epc; > > unsigned long insn; > > unsigned long addr = regs->badaddr; > > - int len = 0, fp = 0; > > + int fp = 0, len = 0, rd = 0; > > > > perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); > > > > @@ -351,67 +333,68 @@ static int handle_scalar_misaligned_store(struct pt_regs *regs) > > > > regs->epc = 0; > > > > - val.data_ulong = GET_RS2(insn, regs); > > - > > - if ((insn & INSN_MASK_SW) == INSN_MATCH_SW) { > > + if (riscv_insn_is_sw(insn)) { > > len = 4; > > -#if defined(CONFIG_64BIT) > > - } else if ((insn & INSN_MASK_SD) == INSN_MATCH_SD) { > > + rd = riscv_insn_sw_extract_xs2(insn); > > + } else if (riscv_insn_is_sd(insn)) { > > len = 8; > > -#endif > > - } else if ((insn & INSN_MASK_FSD) == INSN_MATCH_FSD) { > > + rd = riscv_insn_sd_extract_xs2(insn); > > + } else if (riscv_insn_is_fsd(insn)) { > > fp = 1; > > len = 8; > > - val.data_u64 = GET_F64_RS2(insn, regs); > > - } else if ((insn & INSN_MASK_FSW) == INSN_MATCH_FSW) { > > + rd = riscv_insn_fsd_extract_fs2(insn); > > + } else if (riscv_insn_is_fsw(insn)) { > > fp = 1; > > len = 4; > > - val.data_ulong = GET_F32_RS2(insn, regs); > > - } else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) { > > + rd = riscv_insn_fsw_extract_fs2(insn); > > + } else if (riscv_insn_is_sh(insn)) { > > len = 2; > > -#if defined(CONFIG_64BIT) > > - } else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) { > > + rd = riscv_insn_sh_extract_xs2(insn); > > + } else if (riscv_insn_is_c_sd(insn)) { > > len = 8; > > - val.data_ulong = GET_RS2S(insn, regs); > > - } else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP) { > > + rd = riscv_insn_c_sd_extract_xs2(insn); > > + } else if (riscv_insn_is_c_sdsp(insn)) { > > len = 8; > > - val.data_ulong = GET_RS2C(insn, regs); > > -#endif > > - } else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) { > > + rd = riscv_insn_c_sdsp_extract_xs2(insn); > > + } else if (riscv_insn_is_c_sw(insn)) { > > len = 4; > > - val.data_ulong = GET_RS2S(insn, regs); > > - } else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP) { > > + rd = riscv_insn_c_sw_extract_xs2(insn); > > + } else if (riscv_insn_is_c_swsp(insn)) { > > len = 4; > > - val.data_ulong = GET_RS2C(insn, regs); > > - } else if ((insn & INSN_MASK_C_FSD) == INSN_MATCH_C_FSD) { > > + rd = riscv_insn_c_swsp_extract_xs2(insn); > > + } else if (riscv_insn_is_c_fsd(insn)) { > > fp = 1; > > len = 8; > > - val.data_u64 = GET_F64_RS2S(insn, regs); > > - } else if ((insn & INSN_MASK_C_FSDSP) == INSN_MATCH_C_FSDSP) { > > + rd = riscv_insn_c_fsd_extract_fs2(insn); > > + } else if (riscv_insn_is_c_fsdsp(insn)) { > > fp = 1; > > len = 8; > > - val.data_u64 = GET_F64_RS2C(insn, regs); > > -#if !defined(CONFIG_64BIT) > > Shouldn't we keep this? The ifdef doesn't matter anymore because the new riscv_insn_is_*() have are all ifdef'd out so unconditionally return false if they are not supported on CONFIG_64BIT/CONFIG_32BIT. > > > - } else if ((insn & INSN_MASK_C_FSW) == INSN_MATCH_C_FSW) { > > + rd = riscv_insn_c_fsdsp_extract_fs2(insn); > > + } else if (riscv_insn_is_c_fsw(insn)) { > > fp = 1; > > len = 4; > > - val.data_ulong = GET_F32_RS2S(insn, regs); > > - } else if ((insn & INSN_MASK_C_FSWSP) == INSN_MATCH_C_FSWSP) { > > + rd = riscv_insn_c_fsw_extract_fs2(insn); > > + } else if (riscv_insn_is_c_fswsp(insn)) { > > fp = 1; > > len = 4; > > - val.data_ulong = GET_F32_RS2C(insn, regs); > > -#endif > > - } else if ((insn & INSN_MASK_C_SH) == INSN_MATCH_C_SH) { > > + rd = riscv_insn_c_fswsp_extract_fs2(insn); > > + } else if (riscv_insn_is_c_sh(insn)) { > > len = 2; > > - val.data_ulong = GET_RS2S(insn, regs); > > + rd = riscv_insn_c_sh_extract_xs2(insn); > > } else { > > - regs->epc = epc; > > This line should be kept. Oh huh I wonder why I got rid of this. Good catch, thank you! - Charlie > > Thanks, > Jesse Taube > > > return -1; > > } > > > > if (!IS_ENABLED(CONFIG_FPU) && fp) > > return -EOPNOTSUPP; > > > > + if (!fp) > > + val.data_ulong = *(unsigned long *)((unsigned long *)regs + rd); > > + else if (len == 8) > > + val.data_u64 = get_f64_rs(rd, regs); > > + else > > + val.data_ulong = get_f32_rs(rd, regs); > > + > > if (user_mode(regs)) { > > if (copy_to_user((u8 __user *)addr, &val, len)) > > return -1; > > > > -- > > 2.54.0 > > > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv