From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6CA542F39AB for ; Fri, 3 Jul 2026 03:03:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783047796; cv=none; b=ikcCVIChYiBMcNxK4uOKSPpb0kj8CN8ZGh9lFbSHvUgsar026JHvZNUAh2L2Ft1BBO/HM752Ra/pVATwN31OEArBmHpbPxMktJOp36BtOuk7ydkDBv0y1MgIBvlyhf0RMfzQtdG1m+SGOZLAagB41uc7/+MqEXoiJFUDIhJde9I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783047796; c=relaxed/simple; bh=efnEm+W+VtLCuut/dmb71mCG6+tWP/oTrs9sNNtx4cg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=NHNkiNJFFgZzvxaa0HDKV59rbLy/VTCwybCZ6KLXD6CwTw4H8nj9faqmpgTNrngJqDGoD92FnGcSBuoY3olgbdfw7aZH3vxY3jSd8Xjl96ruZ1x6bm2QjvpcCyBT6aboilk+B5aALaTwbvqKBdBZnEfcbOa29/YGd2xUPSDHCm8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=UjTLuIAs; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="UjTLuIAs" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E48C422D7; Thu, 2 Jul 2026 20:03:08 -0700 (PDT) Received: from localhost (a079125.arm.com [10.164.21.37]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8940F3F673; Thu, 2 Jul 2026 20:03:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783047793; bh=efnEm+W+VtLCuut/dmb71mCG6+tWP/oTrs9sNNtx4cg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=UjTLuIAsvwzssMNef6cyBWug9GJal49GKFuVcxgfGednLxs1e+gG5uETzE3UevRJG +DU0XyVSa1Y29wcDwIHFWKVxrh9p0lS7vbrWqvRJAhxj+yHlqn6/wCF3Yhl4+tD/hu HRSfa/o/e0pTJRrtWJ6Pfl//U2V5lTpdxvcE809k= Date: Fri, 3 Jul 2026 08:33:09 +0530 From: Linu Cherian To: Mark Rutland Cc: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 5/5] arm64: cpufeature: Extend bbml3 support list Message-ID: References: <20260701094131.677636-1-linu.cherian@arm.com> <20260701094131.677636-6-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Hi Mark, On Thu, Jul 02, 2026 at 11:47:04AM +0100, Mark Rutland wrote: > On Wed, Jul 01, 2026 at 03:11:31PM +0530, Linu Cherian wrote: > > Add below cpus to the midr list, which supports > > BBML3 but don't advertise through MMFR2 ID. > > > > Cortex A520(AE) > > Cortex A715 > > Cortex A720(AE) > > Cortex A725 > > Neoverse N3 > > C1-Nano > > C1-Pro > > C1-Ultra > > C1-Premium > > > > Signed-off-by: Linu Cherian > > --- > > arch/arm64/kernel/cpufeature.c | 9 +++++++++ > > 1 file changed, 9 insertions(+) > > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > index d754b1b7da77..9b806c1c60aa 100644 > > --- a/arch/arm64/kernel/cpufeature.c > > +++ b/arch/arm64/kernel/cpufeature.c > > @@ -2142,6 +2142,15 @@ bool cpu_supports_bbml3(void) > > MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), > > MIDR_ALL_VERSIONS(MIDR_AMPERE1), > > MIDR_ALL_VERSIONS(MIDR_AMPERE1A), > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE), > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), > > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), > > + MIDR_ALL_VERSIONS(MIDR_C1_NANO), > > + MIDR_ALL_VERSIONS(MIDR_C1_PRO), > > + MIDR_REV_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf), > > + MIDR_REV_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf), > > Why do these two have a range? The commit message didn't mention this. C1 ultra and C1 Premium has BBM related errata until r1p0. Will mention that in commit message. Thanks, Linu Cherian.