From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3A6CB220F2A for ; Fri, 3 Jul 2026 03:06:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783047980; cv=none; b=U55Sm1Bycmo4PwXGoT+D1blW6eMTjEvWdf/JcTrEAM6uQXTeH+JnFfm8CUzvQywKDJ4XEUTmx4SXsY9rTbHTCuMbXSSX+NbvQkHFY7avxFjnymDyo5iN9Qpz/uxStjEZZ2MT4o/ekpQ9pG2Ysct6r4T0Lxb3Dt4qHSJ3JrX1EiM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783047980; c=relaxed/simple; bh=OU21J2+hdlwMWnIWHQcQ41rGh96YqaiWwRNbVCR+/+Y=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=MqJNFde5Z44BWORzO70Hh5/gtvNpBWmE2Se7GF1GRp9wYV0k8LOA0Q1/bqzuCyTo44eZb6NfZ9+lbKpqPK2UPEetvC3vuWdyg5K2mylevpHFJqAoyMV5oj5QD0O7937r/mSXXcIZGb+a/qCA+zd2xHVesmdkd+ICUQTLFR/qNO0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Qc1t9JIK; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Qc1t9JIK" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 717AD22D7; Thu, 2 Jul 2026 20:06:12 -0700 (PDT) Received: from localhost (a079125.arm.com [10.164.21.37]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 178593F673; Thu, 2 Jul 2026 20:06:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783047976; bh=OU21J2+hdlwMWnIWHQcQ41rGh96YqaiWwRNbVCR+/+Y=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Qc1t9JIKdyKCQCqyqgWpo4J33IE3ANvN4guvB2EKHZdIClVzDpVkMJpFYRlsf21tt YtkIiCALc+JNfrSbV1/OHJ8txg/JNx6Scm7v41NoP0uYvcuHup9VzhrPOhqaXz2nYG 8ju7G+ATbWls/yp5fkfpptS+lfvO3fr5SaseMuow= Date: Fri, 3 Jul 2026 08:36:13 +0530 From: Linu Cherian To: Mark Rutland Cc: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/5] arm64: cpufeature: Detect BBML3 based on MMFR2 ID Message-ID: References: <20260701094131.677636-1-linu.cherian@arm.com> <20260701094131.677636-3-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Hi Mark, On Thu, Jul 02, 2026 at 11:45:14AM +0100, Mark Rutland wrote: > On Wed, Jul 01, 2026 at 03:11:28PM +0530, Linu Cherian wrote: > > Add MMFR2 ID based BBML3 feature detection, so > > that compliant cpus doesn't need to be added to the > > midr list. > > > > Signed-off-by: Linu Cherian > > --- > > arch/arm64/kernel/cpufeature.c | 14 +++++++------- > > arch/arm64/tools/sysreg | 1 + > > 2 files changed, 8 insertions(+), 7 deletions(-) > > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > index 9986eb7b379c..d754b1b7da77 100644 > > --- a/arch/arm64/kernel/cpufeature.c > > +++ b/arch/arm64/kernel/cpufeature.c > > @@ -2133,6 +2133,7 @@ static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, > > > > bool cpu_supports_bbml3(void) > > { > > + u64 mmfr2; > > /* CPUs that support BBML3 but dont advertise through MMFR2 ID */ > > static const struct midr_range supports_bbml3_list[] = { > > MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), > > @@ -2144,15 +2145,14 @@ bool cpu_supports_bbml3(void) > > {} > > }; > > > > - if (!is_midr_in_range_list(supports_bbml3_list)) > > - return false; > > + if (is_midr_in_range_list(supports_bbml3_list)) > > + return true; > > > > - /* > > - * We currently ignore the ID_AA64MMFR2_EL1 register, and only care > > - * about whether the MIDR check passes. > > - */ > > + mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1); > > + if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) == ID_AA64MMFR2_EL1_BBM_3) > > + return true; > > This needs to be '>=', so that if there's a future BBML4, we correctly > detect that CPUs with BBML4 also have the BBML3 behaviour. > > It would also be better to check the ID field first, before falling back > to the MIDR check. That way a reader can more clearly see that > supports_bbml3_list catches older parts that don't advertised BBML3, and > the comment above supports_bbml3_list would be clearer. Okay, agree. -- Thanks, Linu Cherian.