From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out30-111.freemail.mail.aliyun.com (out30-111.freemail.mail.aliyun.com [115.124.30.111]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B03E376468 for ; Fri, 3 Jul 2026 06:01:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.111 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783058509; cv=none; b=Zz1IumUJcKNeJ2wWuG013rE7rF+5zDfJL0DjN6MlIHIpJIEKHtQt7obkZ0OkJ/HoUCGyUq5dKgs0b8INuckBdGYhNQsv7JdWhQMXAezX5ZfLXbwjWUJZz0wHTbzpl0wncyfGkscX5iWxVmIWwXpExDJeKj+w4IkQ+ETqkidAa6c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783058509; c=relaxed/simple; bh=7n2cocoS6wBLbNxMQMhDP0l/KEKVe/1Wt8Yz8fRiiuU=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=YXa2+efFpJoI0y4zh/1f79h8F6FVzWR8AHgoXpVP1pM6iggMdHWCk2Dd768h/2+NkyK0+H/2wmgImw2nksS9/SGZagBHmBJ2fP6c7lxQXMgltisZMvbZm4He0Nh4+Kc3/Ci8g8fig0pjADSkTm/rG/2lcX7vCySeXf1lFuOk1jU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=sjCAEw0Y; arc=none smtp.client-ip=115.124.30.111 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="sjCAEw0Y" DKIM-Signature:v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1783058499; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; bh=t2GSIPSxJh8EZqC8ezwABY7VMBVdrUEd4MP2m61kMJg=; b=sjCAEw0YWvzAJwBsmThe6l0ZcnwujgFDHubNbjJYkMeF8SAYfVKWbKJgPfg34R5iiuD8BEml/MjgwEpa5UOv8vRUfGvJedSEVwjbVs9ctoDIIPeBzU/YiyRwGFsse6EB9bgiDwPv+6hHWZL1KN73ggkGn0lw/MbOH3ZVJIcxQl4= X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R211e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam011083073210;MF=fengwei_yin@linux.alibaba.com;NM=1;PH=DS;RN=22;SR=0;TI=SMTPD_---0X6I6p2n_1783058494; Received: from U-V2QX163P-2032.local(mailfrom:fengwei_yin@linux.alibaba.com fp:SMTPD_---0X6I6p2n_1783058494 cluster:ay36) by smtp.aliyun-inc.com; Fri, 03 Jul 2026 14:01:37 +0800 Date: Fri, 3 Jul 2026 14:01:33 +0800 From: YinFengwei To: Kiryl Shutsemau Cc: Catalin Marinas , Will Deacon , James Morse , Mark Rutland , Marc Zyngier , Doug Anderson , Petr Mladek , Thomas Gleixner , Andrew Morton , Baoquan He , Puranjay Mohan , Usama Arif , Breno Leitao , Julien Thierry , Lecopzer Chen , Sumit Garg , kernel-team@meta.com, kexec@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, "Kiryl Shutsemau (Meta)" Subject: Re: [PATCH v5 0/4] arm64: cross-CPU NMI via SDEI Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Hi Kirill, On Mon, Jun 29, 2026 at 04:07:14PM +0100, Kiryl Shutsemau wrote: > From: "Kiryl Shutsemau (Meta)" > > A class of debug/observability features needs to interrupt a CPU that has > its interrupts locally masked: the all-CPU backtrace behind sysrq-l / > RCU-stall / hung-task / hard-lockup dumps, and crash_smp_send_stop() > capturing a stuck CPU's state into the vmcore. On arm64 these need a > mechanism that reaches a CPU spinning with DAIF masked, which a normal IPI > cannot. > V> arm64 has two such mechanisms today: > > - GICv3 pseudo-NMI (interrupt priority masking). The cost lands on the > interrupt mask/unmask hot path: local_irq_enable() becomes an > ICC_PMR_EL1 write, and exception entry/exit save and restore the PMR, > paid on every CPU whether or not an NMI is ever delivered. > > Measured on Grace (Neoverse V2; ICC_CTLR_EL1.PMHE=0, so the PMR-sync > DSB is already patched to a NOP), pseudo_nmi=0 vs pseudo_nmi=1: > > gettid() loop: 178 -> 253 ns/call (+42%, ~74 ns) > will-it-scale sched_yield: 0.705x throughput, flat from 1 to 72 cores > will-it-scale page_fault1: within ~5% > > The ~74 ns is a fixed per-syscall entry/exit tax -- it reproduces at > +73.5 ns on Neoverse N2 -- so the hit tracks syscall/exception density > and is unacceptable on syscall-bound fleet workloads, which therefore > run with pseudo-NMI disabled. > This patchset works perfectly on our Neoverse N2 ARM64 platform. So Tested-by: Yin Fengwei Regards Yin, Fengwei