From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D24A83D5C12 for ; Fri, 3 Jul 2026 14:48:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783090134; cv=none; b=FQrG7uCQTpRFsorUrWN2EwKpfkTZdp2HJgc/uleRDIzXAhR4+SgdQwSKjU18KBxcCJ/lwwQmnJRtCzw4ijooIluyn368pPRFTftdCXG+SXuHqk60p5ATEuzFSmGN99lMUEDbo5cU1KRGd2MMNE2aIlySivxRFTCX1LDExLAKJi4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783090134; c=relaxed/simple; bh=HqK0apG2WBVp9keeHQN4EfAdivjOtfyBmEcKP8064hw=; h=From:Date:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=riRQIpcselYotoLBdJr7x1aHKzADeDkZvljjPEuRGuEKB9irJ/CtHpsaDMTPBsaL63zFn0+28om6Qv2/xJCwZD8cm/sAFnxFlPh4Xkdb3tJU9EeTKb1I0/6h8icWS4603wnnCtHuwLG2Y8Kty5ZB6DW5I5hs/tzzpLePhVcr018= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b=e+7lz/PP; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b="e+7lz/PP" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-493c52cde9eso6429965e9.3 for ; Fri, 03 Jul 2026 07:48:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1783090131; x=1783694931; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:date:from:from:to:cc:subject:date:message-id:reply-to; bh=RtbeAb4anjju2Gg5Hr2svmQH8LAj1CgUb05x/8fx3ZI=; b=e+7lz/PPnTzecXOAHSvZyU3R8gflwVZHQobEZRvjqS0VJt1OD2OxEdy7uypE1VSXhW Wo2KlJRzSCCadbsZ3g6xor/zF/CAXgJy6mmpT3K1jfMsg8F79YWpFcfLzyeZzCUsqyAv Z38B0wbs9LazAhImGpTwxhyrRbFe+rB6YqhnWSPxRIwvZ6bxF6qt9zg6794DgkVcD8GA 2QwPxfSpHgUdlj55ugttafXDrD1xYpkTFOjhBZqJZtQDe+jOxlrDvErQrG0kxvvBIxxJ L7A0zCVWI1NwbNMbs4zpW+/VO1jsEH50fgePG27cYspi5SJLTDHDEESLHvoSWn3LNgj3 +ruQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783090131; x=1783694931; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:date:from:x-gm-gg:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RtbeAb4anjju2Gg5Hr2svmQH8LAj1CgUb05x/8fx3ZI=; b=puuLizUesJKfqw5/sMC6WQ4MJtXEDYNK8/4tnYHMSAUFGl52CUDWAWrfHd7nmrmmRa CYdNNnNMnE9NN7ZrLMJThZUxqWJWEjRBgywnIYx/kph+OuY7BQudy6jyNLBJffl8Hcqx +j1yURlztvmV+1IQOhOMwMhKLBzlbfdb4FXiFehBOqsfqFXT18pEM1tqijvmzT7jLHVc GfYo2ZqacsOUXz6q5ZlqN79zyPq2UMKfG0MEZBIIL9gQD+6RAEnzX1jRLwRDA5Yimc+W oKy1TWihMehoQDuNOmOm4+PvHT3xVMM8XaLHgrPkrc7ABLTsghSZjsPjAwaUIeY8TcI9 6ZiA== X-Forwarded-Encrypted: i=1; AFNElJ8lHxSjJkRt0uM2L4t8/xcE/AwsUsF2roh9fgyXsrtuGV9S5dspqAoknDE2/oMiwxvoyezY/s7jY9HpGNc=@vger.kernel.org X-Gm-Message-State: AOJu0YyiXaKF4H3kLeXez9rh32k1XQ74eXZEUUjb9F9GjokGFAm5kkW4 x0IFAaXw+xrQF7XewoYuSUVtRfci9RZTovGSXi5fYMprzjSBZLVb3c48ZA6TzXho6Dc= X-Gm-Gg: AfdE7cmk0P3zFobY4haNEg3BObNXnxX1vAGYZfqvZmCWv5GeKBkhHYidZut+7gDPvjH is2CxaCse6QqwMa59sd2cZZnlugBxZQQtOSL5WNTPkawn7WdcHVXYJ9Yt3uJXIl/hpRX+LeN7Xb LPrhg/I9goRk14AZaCBhYd50OvQDzqyIOHgOS0lQRbVBqisoGrHXTwn07UzncRfkbyGpQLu9vzk ImRXvXF5+d96e0dlBdtkcrEhdjuHKrcDl0wZDYAzCGO7pMP+bdJvljLEcYeS3p4J0p+INDm5Igm kdWIQNJ4h9PFiq0Hb+aOAhWFhVm/GGnE0sMXqWVe1nWQC4QngcSIWeeczWJAa04+cX+KKMinoLN HBAPeF3jeZ9KAvc9sUf++8bXYSU+chipM9XJUAo8EVrLhdPdGcgvGGCZRJ48pJcJyk7siveDBNI NDi1dQOg/Wx3w= X-Received: by 2002:a05:600c:34c5:b0:493:bc4a:e7d3 with SMTP id 5b1f17b1804b1-493d0f4efa6mr1735385e9.39.1783090131280; Fri, 03 Jul 2026 07:48:51 -0700 (PDT) Received: from localhost ([195.94.145.62]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-493c637568dsm149767675e9.4.2026.07.03.07.48.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2026 07:48:50 -0700 (PDT) From: Andrea della Porta X-Google-Original-From: Andrea della Porta Date: Fri, 3 Jul 2026 16:52:17 +0200 To: Sean Young Cc: Andrea della Porta , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , linux-pwm@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Naushir Patuck , Stanimir Varbanov , mbrugger@suse.com Subject: Re: [PATCH v5 2/3] pwm: rp1: Add RP1 PWM controller driver Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Hi Sean, On 15:29 Fri 12 Jun , Sean Young wrote: > On Fri, Jun 12, 2026 at 04:01:27PM +0200, Andrea della Porta wrote: > > From: Naushir Patuck > > > > The Raspberry Pi RP1 southbridge features an embedded PWM > > controller with 4 output channels, alongside an RPM interface > > to read the fan speed on the Raspberry Pi 5. > > > > Add the supporting driver. > > <...snip...> > > I don't understand the point of the clk_enabled field. If the probe > function succeeds, then clk_enabled = true. It is set to false during > suspend, but after suspend the only thing which can follow is resume, > I think. In resume, we set it in to true again unconditionally. So > it is always true, no? It's true unless enabling the clock again in rp1_pwm_resume() will fail. That will trap the unbalanced condition mentioned by Uwe in: https://lore.kernel.org/all/adiW1tBC8Imd14LD@monoceros/ > > > +}; > > + > > +struct rp1_pwm_waveform { > > + u32 period_ticks; > > + u32 duty_ticks; > > + bool enabled; > > + bool inverted_polarity; > > +}; > > + <...snip...> > > + > > + /* > > + * The period is limited to U32_MAX, and it will be decremented by one later > > + * to allow 100% duty cycle. > > + */ > > + if (period_ticks > U32_MAX) { > > + period_ticks = U32_MAX; > > + } else if (period_ticks < 2) { > > + period_ticks = 2; > > + ret = 1; > > + } > > period_ticks = clamp(period_ticks, 2, U32_MAX); > > Although that misses out the `ret = 1;` which I am not sure about anyway. But we need that ret = 1 to announce that values have been rounded. > > > + > > + duty_ticks = mul_u64_u64_div_u64(wf->duty_length_ns, clk_rate, NSEC_PER_SEC); > > + duty_ticks = min(duty_ticks, period_ticks); > > + offset_ticks = mul_u64_u64_div_u64(wf->duty_offset_ns, clk_rate, NSEC_PER_SEC); > > + if (offset_ticks >= period_ticks) > > + offset_ticks %= period_ticks; > > + if (duty_ticks && offset_ticks && > > + ret = dev_err_probe(dev, -EINVAL, "Clock rate > 1 GHz is not supported\n"); <...snip...> > > + goto err_disable_clk; > > + } > > + rp1->clk_rate = clk_rate; > > + > > + chip->ops = &rp1_pwm_ops; > > Can we add the following please: > > chip->atomic = true; > > This means that the pwm can be controlled from atomic context (not process > context) using pwm_apply_atomic(). This is very helpful for the pwm-ir-tx > driver, which produces a much more faithful IR signal in atomic context. > > Using pwm for infrared tx is much nicer than using gpio which bit bangs > the IR signal and holds the CPU with interrupts disabled for upto one second. > > As far as I can see there is no sleeping code in these code paths, so we > should be fine. Sure, added. Many thanks, Andrea > > Thanks, > > Sean > <...snip...>