From: Breno Leitao <leitao@debian.org>
To: K Prateek Nayak <kprateek.nayak@amd.com>
Cc: Andrea Righi <arighi@nvidia.com>, Ingo Molnar <mingo@redhat.com>,
Peter Zijlstra <peterz@infradead.org>,
Juri Lelli <juri.lelli@redhat.com>,
Vincent Guittot <vincent.guittot@linaro.org>,
Dietmar Eggemann <dietmar.eggemann@arm.com>,
Steven Rostedt <rostedt@goodmis.org>,
Ben Segall <bsegall@google.com>, Mel Gorman <mgorman@suse.de>,
Valentin Schneider <vschneid@redhat.com>,
Christian Loehle <christian.loehle@arm.com>,
Phil Auld <pauld@redhat.com>, Koba Ko <kobak@nvidia.com>,
Felix Abecassis <fabecassis@nvidia.com>,
Balbir Singh <balbirs@nvidia.com>,
Joel Fernandes <joelagnelf@nvidia.com>,
Shrikanth Hegde <sshegde@linux.ibm.com>,
linux-kernel@vger.kernel.org
Subject: Re: kmemleak: sched_domain_shared leaked on asymmetric-capacity + SCHED_CACHE
Date: Fri, 3 Jul 2026 09:19:42 -0700 [thread overview]
Message-ID: <akfg6wBsfORgYhTQ@gmail.com> (raw)
In-Reply-To: <73685ae1-6d90-4799-a1d7-08a1fcf24b8b@amd.com>
Hello Prateek,
On Fri, Jul 03, 2026 at 04:05:59PM +0530, K Prateek Nayak wrote:
> On 7/3/2026 3:52 PM, Breno Leitao wrote:
> > On current linux-next (CONFIG_SCHED_CACHE=y) we hit a kmemleak on an
> > arm64 box with asymmetric CPU capacity, triggered by a cpuset-driven
> > sched-domain rebuild:
> >
> > kmemleak: unreferenced object 0xffff000100c95e80 (size 32):
> > comm "kworker/22:1", pid 407, jiffies 4294669077
> > hex dump (first 32 bytes):
> > 48 00 00 00 48 00 00 00 00 00 00 00 20 00 00 00 H...H....... ...
> > backtrace (crc ec5d7053):
> > __kmalloc_cache_node_noprof
> > build_sched_domains
> > partition_sched_domains
> > rebuild_sched_domains_locked
> > rebuild_sched_domains
> > process_scheduled_works
> > kthread
> > ret_from_fork
> > kmemleak: 1 new suspected memory leaks
> >
> > The leaked object is a struct sched_domain_shared (32 bytes with
> > CONFIG_SCHED_CACHE) allocated in __sds_alloc(), inlined into
> > build_sched_domains()
> >
> > Is this a known issue?
>
> It is theoretically possible but there is a defensive WARN_ON()
> in topology code that you should have hit first. Do you see any
> other warning?
>
> If it is not too much trouble, could you add "sched_verbose"
> to your kernel cmdline (or do
> echo Y > /sys/kernel/debug/sched/verbose) and redo this cpuset
> that leaks the data and share the dmesg. It should give some clue
> what the topology looks like that causes this.
Sure, does this one help:
bash-5.1# cat /sys/kernel/debug/kmemleak
unreferenced object 0xffff0000c1180820 (size 32):
comm "swapper/0", pid 1, jiffies 4294667323
hex dump (first 32 bytes):
08 00 00 00 08 00 00 00 00 00 00 00 20 00 00 00 ............ ...
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
backtrace (crc f4478cb7):
kmemleak_alloc+0x44/0xd8
__kmalloc_cache_node_noprof+0x344/0x5d8
build_sched_domains+0x2f8/0x2110
sched_init_domains+0xec/0x160
sched_init_smp+0x48/0x108
kernel_init_freeable+0x140/0x200
kernel_init+0x30/0x170
ret_from_fork+0x10/0x20
bash-5.1# cd /sys/kernel/debug/sched/domains/
bash-5.1# grep . -r *
cpu0/domain0/level:1
cpu0/domain0/flags:SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_ASYM_CPUCAPACITY SD_ASYM_CPUCAPACITY_FULL SD_SHARE_LLC SD_PREFER_SIBLING
cpu0/domain0/name:MC
cpu0/domain0/cache_nice_tries:1
cpu0/domain0/imbalance_pct:117
cpu0/domain0/busy_factor:16
cpu0/domain0/max_newidle_lb_cost:2127
cpu0/domain0/max_interval:16
cpu0/domain0/min_interval:8
cpu1/domain0/level:1
cpu1/domain0/flags:SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_ASYM_CPUCAPACITY SD_ASYM_CPUCAPACITY_FULL SD_SHARE_LLC SD_PREFER_SIBLING
cpu1/domain0/name:MC
cpu1/domain0/cache_nice_tries:1
cpu1/domain0/imbalance_pct:117
cpu1/domain0/busy_factor:16
cpu1/domain0/max_newidle_lb_cost:18112
cpu1/domain0/max_interval:16
cpu1/domain0/min_interval:8
cpu2/domain0/level:1
cpu2/domain0/flags:SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_ASYM_CPUCAPACITY SD_ASYM_CPUCAPACITY_FULL SD_SHARE_LLC SD_PREFER_SIBLING
cpu2/domain0/name:MC
cpu2/domain0/cache_nice_tries:1
cpu2/domain0/imbalance_pct:117
cpu2/domain0/busy_factor:16
cpu2/domain0/max_newidle_lb_cost:3147
cpu2/domain0/max_interval:16
cpu2/domain0/min_interval:8
cpu3/domain0/level:1
cpu3/domain0/flags:SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_ASYM_CPUCAPACITY SD_ASYM_CPUCAPACITY_FULL SD_SHARE_LLC SD_PREFER_SIBLING
cpu3/domain0/name:MC
cpu3/domain0/cache_nice_tries:1
cpu3/domain0/imbalance_pct:117
cpu3/domain0/busy_factor:16
cpu3/domain0/max_newidle_lb_cost:16399
cpu3/domain0/max_interval:16
cpu3/domain0/min_interval:8
cpu4/domain0/level:1
cpu4/domain0/flags:SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_ASYM_CPUCAPACITY SD_ASYM_CPUCAPACITY_FULL SD_SHARE_LLC SD_PREFER_SIBLING
cpu4/domain0/name:MC
cpu4/domain0/cache_nice_tries:1
cpu4/domain0/imbalance_pct:117
cpu4/domain0/busy_factor:16
cpu4/domain0/max_newidle_lb_cost:27180
cpu4/domain0/max_interval:16
cpu4/domain0/min_interval:8
cpu5/domain0/level:1
cpu5/domain0/flags:SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_ASYM_CPUCAPACITY SD_ASYM_CPUCAPACITY_FULL SD_SHARE_LLC SD_PREFER_SIBLING
cpu5/domain0/name:MC
cpu5/domain0/cache_nice_tries:1
cpu5/domain0/imbalance_pct:117
cpu5/domain0/busy_factor:16
cpu5/domain0/max_newidle_lb_cost:18384
cpu5/domain0/max_interval:16
cpu5/domain0/min_interval:8
cpu6/domain0/level:1
cpu6/domain0/flags:SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_ASYM_CPUCAPACITY SD_ASYM_CPUCAPACITY_FULL SD_SHARE_LLC SD_PREFER_SIBLING
cpu6/domain0/name:MC
cpu6/domain0/cache_nice_tries:1
cpu6/domain0/imbalance_pct:117
cpu6/domain0/busy_factor:16
cpu6/domain0/max_newidle_lb_cost:16261
cpu6/domain0/max_interval:16
cpu6/domain0/min_interval:8
cpu7/domain0/level:1
cpu7/domain0/flags:SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_ASYM_CPUCAPACITY SD_ASYM_CPUCAPACITY_FULL SD_SHARE_LLC SD_PREFER_SIBLING
cpu7/domain0/name:MC
cpu7/domain0/cache_nice_tries:1
cpu7/domain0/imbalance_pct:117
cpu7/domain0/busy_factor:16
cpu7/domain0/max_newidle_lb_cost:7780
cpu7/domain0/max_interval:16
cpu7/domain0/min_interval:8
next prev parent reply other threads:[~2026-07-03 16:20 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-09 18:07 [PATCH v6 0/5 RESEND] sched/fair: SMT-aware asymmetric CPU capacity Andrea Righi
2026-05-09 18:07 ` [PATCH 1/5] sched/fair: Drop redundant RCU read lock in NOHZ kick path Andrea Righi
2026-05-11 13:04 ` Vincent Guittot
2026-05-15 6:49 ` Shrikanth Hegde
2026-05-16 5:45 ` Andrea Righi
2026-05-16 17:15 ` Shrikanth Hegde
2026-05-20 8:34 ` [tip: sched/core] " tip-bot2 for Andrea Righi
2026-05-21 19:47 ` [PATCH 1/5] " Marek Szyprowski
2026-05-21 20:13 ` Andrea Righi
2026-05-09 18:07 ` [PATCH 2/5] sched/fair: Attach sched_domain_shared to sd_asym_cpucapacity Andrea Righi
2026-05-11 13:04 ` Vincent Guittot
2026-05-15 10:05 ` Shrikanth Hegde
2026-05-16 5:58 ` [PATCH v2 " Andrea Righi
2026-05-16 17:19 ` Shrikanth Hegde
2026-05-18 20:58 ` Peter Zijlstra
2026-05-18 21:31 ` Andrea Righi
2026-05-19 5:52 ` K Prateek Nayak
2026-05-19 6:43 ` Andrea Righi
2026-05-19 7:47 ` K Prateek Nayak
2026-05-19 7:54 ` Andrea Righi
2026-05-19 8:46 ` Peter Zijlstra
2026-05-19 11:27 ` K Prateek Nayak
2026-05-19 11:47 ` Peter Zijlstra
2026-05-25 8:30 ` Chen, Yu C
2026-05-20 8:34 ` [tip: sched/core] " tip-bot2 for K Prateek Nayak
2026-07-03 10:22 ` kmemleak: sched_domain_shared leaked on asymmetric-capacity + SCHED_CACHE Breno Leitao
2026-07-03 10:35 ` K Prateek Nayak
2026-07-03 16:19 ` Breno Leitao [this message]
2026-07-04 6:16 ` K Prateek Nayak
2026-05-09 18:07 ` [PATCH 3/5] sched/fair: Prefer fully-idle SMT cores in asym-capacity idle selection Andrea Righi
2026-05-11 13:07 ` Vincent Guittot
2026-05-11 13:45 ` Andrea Righi
2026-05-11 14:25 ` [PATCH v2 " Andrea Righi
2026-05-20 8:34 ` [tip: sched/core] " tip-bot2 for Andrea Righi
2026-05-09 18:07 ` [PATCH 4/5] sched/fair: Reject misfit pulls onto busy SMT siblings on asym-capacity Andrea Righi
2026-05-11 13:07 ` Vincent Guittot
2026-05-15 10:09 ` Shrikanth Hegde
2026-05-16 9:04 ` Andrea Righi
2026-05-20 8:34 ` [tip: sched/core] " tip-bot2 for Andrea Righi
2026-05-09 18:07 ` [PATCH 5/5] sched/fair: Add SIS_UTIL support to select_idle_capacity() Andrea Righi
2026-05-11 13:08 ` Vincent Guittot
2026-05-20 8:34 ` [tip: sched/core] " tip-bot2 for K Prateek Nayak
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