From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D3738436BFC for ; Mon, 6 Jul 2026 18:20:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783362055; cv=none; b=uY+LIfmVgnvKvdtvRohAbNtX1y1cewE2DuZ0NO1WCZIPdG0WunXqDDM3eS1Pp2w4WLZXH/agemAhZhdiD3YLzfHROWxFI+bMddplybI3DxZFsieUS7yEnsQGZEo5KxW/MPOUQhP9tmIDEAZKu+8PiY3KSAccozDxl+x4wobOO1Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783362055; c=relaxed/simple; bh=sakR/mUF17O2uJtIDze5qohEXx2DQJaPiUpFEvm4Ctg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ntAjjDZNOY3pN/RmLzwFLVL25KIGqUBl6aJ/S5dnx/3qeg/yOhE1BG7uSPcm5mo4bhac8tRXSQuZhIjDuh8ZwSsMNqUY3akMjqePoaaV5VXt4NK5A+CTE9AIf957/PNv75OtcyOsmxxBl8D00gJmzIxYKvSqPs1ZY8DyiCR5Bvs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=tyVXaCjg; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="tyVXaCjg" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D4821176C; Mon, 6 Jul 2026 11:20:48 -0700 (PDT) Received: from e129823.arm.com (e129823.arm.com [10.2.213.3]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 915953F905; Mon, 6 Jul 2026 11:20:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783362053; bh=sakR/mUF17O2uJtIDze5qohEXx2DQJaPiUpFEvm4Ctg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=tyVXaCjgwCDhSuPOYrSDVMdnpSTGR+lWm5ldnHAfi9/cvtEtvadXkf2WhFIyBlS8d RAqWlT9Vr64Qd5QEi+mzbYB4pM3hbITByTgmDIIDLCpXmyHkdo6HYDT+i0A6CL0kHO xDjH0B1nKTxSkK8gg3kWJh6wQD4K1Hi+lFGM/1mA= Date: Mon, 6 Jul 2026 19:20:48 +0100 From: Yeoreum Yun To: Leo Yan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, jie.gan@oss.qualcomm.com Subject: Re: [PATCH v8 08/13] coresight: etm4x: fix inconsistencies with sysfs configuration Message-ID: References: <20260629090007.1718746-1-yeoreum.yun@arm.com> <20260629090007.1718746-9-yeoreum.yun@arm.com> <20260706173940.GB1024232@e132581.arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260706173940.GB1024232@e132581.arm.com> Hi Leo, > On Mon, Jun 29, 2026 at 10:00:01AM +0100, Yeoreum Yun wrote: > > [...] > > > @@ -922,25 +950,7 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa > > { > > struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > > struct etm4_enable_arg arg = { }; > > - unsigned long cfg_hash; > > - int ret, preset; > > - > > - /* enable any config activated by configfs */ > > - cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset); > > - if (cfg_hash) { > > - ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); > > - if (ret) { > > - etm4_release_trace_id(drvdata); > > - return ret; > > - } > > - } > > - > > - raw_spin_lock(&drvdata->spinlock); > > - > > - drvdata->trcid = path->trace_id; > > - > > - /* Tracer will never be paused in sysfs mode */ > > - drvdata->paused = false; > > + int ret; > > > > /* > > * Executing etm4_enable_hw on the cpu whose ETM is being enabled > > @@ -948,20 +958,20 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa > > */ > > arg.drvdata = drvdata; > > arg.path = path; > > + > > + raw_spin_lock(&drvdata->spinlock); > > + arg.config = drvdata->config; > > + raw_spin_unlock(&drvdata->spinlock); > > + > > ret = smp_call_function_single(drvdata->cpu, > > etm4_enable_sysfs_smp_call, &arg, 1); > > if (!ret) > > ret = arg.rc; > > if (!ret) > > - drvdata->sticky_enable = true; > > - > > - if (ret) > > + dev_dbg(&csdev->dev, "ETM tracing enabled\n"); > > + else > > etm4_release_trace_id(drvdata); > > > > - raw_spin_unlock(&drvdata->spinlock); > > - > > - if (!ret) > > - dev_dbg(&csdev->dev, "ETM tracing enabled\n"); > > return ret; > > } > > This is most valuable change for me, as now we will have much clear > scope for what is protected ("drvdata->config"). > > However, a corner case was mentioned by Sashiko: > > | It appears etm4_enable_hw() modifies drvdata->ss_status while executing > | via IPI, but sshot_ctrl_store() can modify the same array concurrently > | from process context since the lock is no longer held across the > | smp_call_function_single() call. > > "drvdata->ss_status" is a race condition between SMP call and sysfs > knobs. Should we change to spinlock_irqsave/irqrestore when access > drvdata->ss_status? I know this, but This is currently ignorable since whatever perf or sysfs session, the ss_status is always clear the PENDING and STATUS bits (and we make a compromise for this right now). And the sshot_ctrl_store()'s action is always clear above bits. So, This is ignorable comment from Sashiko. Thanks! -- Sincerely, Yeoreum Yun