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[2003:f6:5f47:db04:37b4:d928:ee3e:b6f8]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-493e0f41014sm30858915e9.6.2026.07.07.00.13.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jul 2026 00:13:10 -0700 (PDT) Date: Tue, 7 Jul 2026 09:13:09 +0200 From: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= To: Rosen Penev Cc: linux-gpio@vger.kernel.org, Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , open list Subject: Re: [PATCHv2] gpio: mvebu: fix devres LIFO ordering between GPIO chip and IRQ domain Message-ID: References: <20260706232223.774895-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="hr5mygvtcaxfa33e" Content-Disposition: inline In-Reply-To: <20260706232223.774895-1-rosenp@gmail.com> --hr5mygvtcaxfa33e Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCHv2] gpio: mvebu: fix devres LIFO ordering between GPIO chip and IRQ domain MIME-Version: 1.0 On Mon, Jul 06, 2026 at 04:22:23PM -0700, Rosen Penev wrote: > During driver removal, devres cleans up in LIFO order. The IRQ domain > was created and its devm cleanup action registered after > devm_gpiochip_add_data(), so the domain was destroyed before the GPIO > chip was deregistered. If gpiod_to_irq() is called on a pin during > this window, mvebu_gpio_to_irq() passes the freed mvchip->domain to > irq_create_mapping(). Without having looked at your patch, I would expect that there is a similar window during probe where calling gpiod_to_irq() between devm_gpiochip_add_data() and IRQ domain creation results in an invalid mvchip->domain being passed to irq_create_mapping(), right? > Fix by moving the IRQ domain creation, devm cleanup action registration, > generic chip allocation, and chip type setup before > devm_gpiochip_add_data(). This ensures the GPIO chip is torn down > first (preventing new IRQ mappings), then the IRQ domain is removed, > and finally mvchip is freed. >=20 > Fixes: 644ee70267a9 ("gpio: mvebu: fix irq domain leak") If the above is right, the referenced commit only creates the issue at driver detach. The issue at probe time exists since=20 fefe7b092345 ("gpio: introduce gpio-mvebu driver for Marvell SoCs") which has `gpiochip_add(&mvchip->chip);` before coping for irqs. Best regards Uwe --hr5mygvtcaxfa33e Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEP4GsaTp6HlmJrf7Tj4D7WH0S/k4FAmpMpwMACgkQj4D7WH0S /k6PkQf/cjApnE5nXUCQ8GAQc8ZrWWggNhmY6A0+vciz1er1sQwxQrcXOEn2jNl4 XVW+M0TE8l8VoYsFQZxLgZm/6FUuyCGcwejFvKD6yFlyebtO6WIp8yS0H//6Gj24 F6nwP1fQ9CCLvGKpv3A829p+wP1+VVnqkWbCFc3aueAov5oLlBaa4Fxe8eAHWFng TNdZ+qlRjfypuRFwp9xV6qFrWnw5O9ghuqFDu+BOy4qlxdLYC4WNizu5N8GwvDgp yp+YYtDCOWZ/UNVxGtCXdzWJHY/r+mW7cidAXNDswkmq7VAu7YCs6G6Qkx0ZLiTj b4TFO5TAuWvLJyBK13Mj3/A/lsx5Lg== =vBwG -----END PGP SIGNATURE----- --hr5mygvtcaxfa33e--