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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b291e189c7sm2365363e87.57.2026.07.20.07.17.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2026 07:17:07 -0700 (PDT) Date: Mon, 20 Jul 2026 17:17:05 +0300 From: Dmitry Baryshkov To: Cristian Ciocaltea Cc: Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov , kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Thomas =?iso-8859-1?Q?Niederpr=FCm?= , Simon Wright Subject: Re: [PATCH v4 4/8] phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes Message-ID: References: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> <20260612-hdptx-clk-fixes-v4-4-ce5e1d456cda@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260612-hdptx-clk-fixes-v4-4-ce5e1d456cda@collabora.com> X-Proofpoint-ORIG-GUID: Jylxioqf1dtqm2bg_XSrluwXwoBw9ynX X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIwMDE1OSBTYWx0ZWRfX78E4QUgoxMSg ktrsUQzDWBkQ0ZtyESmTlm62kWLm+k/5pYsH5huUKFZLgK2ERXtlpe3Q1NOW6tq4wckCFf2z/B0 Hm2M2vXS3f9fkz+CjREAw4cwbkPYjew= X-Authority-Analysis: v=2.4 cv=G58s1dk5 c=1 sm=1 tr=0 ts=6a5e2de6 cx=c_pps a=P2rfLEam3zuxRRdjJWA2cw==:117 a=xqWC_Br6kY4A:10 a=8nJEP1OIZ-IA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=QX4gbG5DAAAA:8 a=shz021jzHIKqnGQv9qIA:9 a=3ZKOabzyN94A:10 a=wPNLvfGTeEIA:10 a=ODZdjJIeia2B_SHc_B0f:22 a=AbAUZ8qAyYyZVLSsDulk:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIwMDE1OSBTYWx0ZWRfX+JsxtA/XeP87 i0432718viygs21kepspKpaIv3s3esCoMIKekNKBia/tfUW3D7Gg7Q5n9D3R7as8xTqgMI/BBOw x6B9Cwry4CcbZqpKXQIWuXjtsnE0joiXOBFqrYgc30Mec8yVxHbg5RmGNJ0lh3bJXBSWF3Z7qkX 3dZRh0LlGWLJK3mt3wwpq0yW6xzgcjxejK1rRjj2MnGo6/emoJilO35I8LnTLIL+RwDmTncJH78 +GO91P0yCWlEIPJUQCZxiDWdjwDuPOeIvjYUhoqIRCRQ2DvhIEV5GbbFAzTZwAWHadGnRgVRrC7 jZHwBthq0T996r1TM5lgL5ZNfXyYIStGTSGng6kd+F0a0CNjyEpfntL2VqEvbhFeXAtdU/sWBlw 3anlvT+QziAjXkniXpcm9qRXayEmCcGS2OY3f1EBRlkZuBHfa/Fe0lJgCreW1NRkv7YmXrKBJLB jOgp9PdVVxqX7XYEDug== X-Proofpoint-GUID: Jylxioqf1dtqm2bg_XSrluwXwoBw9ynX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_03,2026-07-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 phishscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607200159 On Fri, Jun 12, 2026 at 02:45:23AM +0300, Cristian Ciocaltea wrote: > Any changes to the PHY link rate and/or color depth done via the HDMI > PHY configuration API are not immediately programmed into the hardware, > but are delayed until the PHY usage count gets incremented from 0 to 1, > that is when it is powered on or when the PLL clock exposed through > the CCF API is prepared, whichever comes first. Why do you need either-of here? Can it be just one path? > > Since the clock might remain in prepared state after subsequent PHY > config changes, the programming can also be triggered via > clk_ops.set_rate(). However, from the clock consumer perspective (i.e. > VOP2 display controller), the (pixel) clock rate doesn't vary with bpc, > as that is handled internally by the PHY and reflected in the TDMS > character rate only. > > As a consequence, changing the bpc while preserving the modeline may > lead to out-of-sync issues between CCF and HDMI PHY config state, > because the .set_rate() callback is not invoked when clock rate remains > constant. This may also happen when the PHY PLL has been pre-programmed > by an external entity, e.g. the bootloader, which is actually a > regression introduced by the recent FRL patches. > > Introduce a pll_config_dirty flag to keep track of uncommitted PHY > config changes and use it in clk_ops.determine_rate() to invalidate the > current clock rate (as known by CCF) and, consequently, ensure those > changes are programmed into hardware via clk_ops.set_rate(). > > Moreover, proceed with a similar fix in phy_ops.power_on() callback, to > handle the scenario where the CCF API is not used due to operating in > FRL mode, while the clock is still in a prepared state and thus > preventing rk_hdptx_phy_consumer_get() to apply the updated PHY > configuration. > > Fixes: de5dba833118 ("phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support") > Fixes: 9d0ec51d7c22 ("phy: rockchip: samsung-hdptx: Add high color depth management") > Tested-by: Thomas Niederprüm > Tested-by: Simon Wright > Signed-off-by: Cristian Ciocaltea > --- > drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 84 +++++++++++++---------- > 1 file changed, 48 insertions(+), 36 deletions(-) > > diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > index b210c1a88b25..25bd821cd039 100644 > --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > @@ -413,6 +413,7 @@ struct rk_hdptx_phy { > > /* clk provider */ > struct clk_hw hw; > + bool pll_config_dirty; Which lock protects it? > bool restrict_rate_change; > > atomic_t usage_count; -- With best wishes Dmitry