Re: VMX Preemption Timer appears to be buggy on SKX, CLX, and ICX

[Chao Gao <chao.gao@intel.com>]

On Mon, Jul 20, 2026 at 10:35:46AM -0700, Jim Mattson wrote:
>On Mon, Jul 20, 2026 at 3:04 AM Chao Gao <chao.gao@intel.com> wrote:
>>
>> On Fri, Jun 12, 2026 at 03:51:56PM -0700, Jim Mattson wrote:
>> >On Thu, Jun 4, 2026 at 10:56 PM Chao Gao <chao.gao@intel.com> wrote:
>> >>
>> >> On Thu, Jun 04, 2026 at 10:34:40PM -0700, Jim Mattson wrote:
>> >...
>> >> >With respect to EMR, you wrote previously, "A mitigation for this
>> >> >erratum is for software to program the VMX preemption timer for values
>> >> >below 2^25 * CPUID.15H:EBX[31:0] / CPUID.15H:EAX[31:0]."
>> >> >
>> >> >My question is whether the exponent, 25, is a fixed value for all
>> >> >CPUs, regardless of their IA32_VMX_MISC[4:0]. It sounds like you are
>> >> >saying that the exponent may depend on IA32_VMX_MISC[4:0].
>> >>
>> >> Let me double-check this with the internal team and get back to you.
>> >
>> >Have you discovered anything?
>>
>> I just got the final answer:
>>
>> 2^25*M/N is the max value of VMX preemption timer for _all_ affected
>> processors.  Our expectation is that for processors that have different
>> value it will have the issue fixed (VMX preemption timer will implement
>> full 32-bit). Use of 2^25*M/N will still be fine.
>>
>> where M is CPUID.15H:EBX[31:0] and N is CPUID.15H:EAX[31:0].
>
>Great!
>
>How will software identify processors that have the issue fixed?

That isn't clear at the moment.