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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?1A/mU8pA0ygfckY2sCN2I04DgZn2ILnf0jC/p/oJ7aElMQn+FN5zc4N9+3Za?= =?us-ascii?Q?txEDroiSOVKoBwT7sQmMTuHJX0rO+p4AjviJ9zc/eAdAiKbT8lc7702Q5wF6?= =?us-ascii?Q?cmWCjzUEeGhFnzJX0ISqddwy8DjtCV0lqUVmJ3DdP5tWfkCNcVfA+aLTIdF4?= =?us-ascii?Q?DPKsmRQb1GQLU2lhsO1Vury7q+AAOUS2tVZJDUYq4vbges0iBU5S6IMGEGhS?= =?us-ascii?Q?JLqD2z0SDaMNSBgtad762zXdXaph5Kb9be/W7f943bkuDeb6n1lw4hN77Zvh?= =?us-ascii?Q?RHyqQ6QDm2RyacjIMIMuOnAd9gucq+leP3/h9pxT3wFTlbF5jM8fa9IF7O31?= =?us-ascii?Q?+3LCzT8rtLQqz+mhdYyg+/pTDedbSbcPdSA85kzHn7phaAYZUr4xhWqTMtmo?= =?us-ascii?Q?u7c0fn5HtucRC+HMbNHZv6La4jltJH+tQMohgNAVXsadrBiAKShe0QLnJ45G?= =?us-ascii?Q?R6Bzb9qobqWjOY6pGWgMeW2aUuYjG7hnXz53G3EXstZgaRwgBy/5BgtVB1In?= =?us-ascii?Q?v30HGyAW7upVSaCm4fTAWsu45Wm729SW+tIU+Hf4Z3laqCmBdmmsmxEsShtI?= =?us-ascii?Q?u55sTOX0eZQKjtEsU6AT1FSTZ6OIozH+CFZcdx96FZUrx+4aKIAaGU1gA1w6?= =?us-ascii?Q?di/RsBhWwp+7J2DkuqGmCz2gr/fGaqfkOTjk+3zEv0eBonOYstlHB5H3+EuU?= =?us-ascii?Q?YFFcV9uewyLyMLkJ+WlXxHUTFptxS1Vlv++PGrkMvQqwhbTvok7/ykPCXI//?= =?us-ascii?Q?Hotu0Llkoy8Fwib6UMzq2FVG7mMKDfdEMhXJROMZx+DaZzmoPpbIj3Qe0Vxc?= =?us-ascii?Q?ebssoupCBr5qxtUqDmwNxDd807UsmevX5mbP6Ve3HwswK1Zztjcy3Cn3owgn?= =?us-ascii?Q?EQG63ehRc5ZM0fKxTI6cLnI0kaw+2PBHtTE1wjGpKi+w+F/1BwQuA3Q8Dlcx?= =?us-ascii?Q?VxiLCZwd71OfJRFwCQFYJwajBn/27uMOdPaMaE6JnJDi8y4SDeYPmka+jJ1k?= =?us-ascii?Q?OIagXPg5DErnTpDY8lkTgEwQkVchKFIf0WsD2Yc0I51IXY+4pqqSeLL+H1bn?= =?us-ascii?Q?f4X9A34ro/WJp8WOxGeKTja2ZSofVHdBqqDnGd91Jhgp5Ev+Ve3041VJoh0Q?= =?us-ascii?Q?jKTMtpF66Cd35EHuRAP+1Q9wWrQYtvhye4VFLpcWTW0d9KmjvNdbN39d2ElY?= =?us-ascii?Q?w4Gb5vVfagt5D1vFHEb7mrEA2C8U8DtnxOVysgk5YzLRHc8kJ1FNzV8LEsv0?= =?us-ascii?Q?V7+y3tpCoYq6/0PgPAfv2/xp+7Uv/ZojxE4V+bR1KaLkEIXFeh4m/OnMdmCN?= =?us-ascii?Q?w/yV4xbpHuesuBpvoNo2F1gq2OYGuwhD1IKpPFIqdEP4cfrr0umYj50XjfN6?= =?us-ascii?Q?U06yaIoUHEDYY2YjbEpfXZDkwA+8dc10yhW09P8uU8LDV0kg75XL8N1++toj?= =?us-ascii?Q?G0EMqH/N5v0fqbCQ0MNCpR3IYGx+J7++RxDfFmBvB6FGMyWlHqEcbprF6iHr?= =?us-ascii?Q?TfjA8yR3vUEKEf81YVp3otgcP1yKxeJdOz2rA2Q7uFJGd+zukeBdO3OYzqFJ?= =?us-ascii?Q?4jJV8GEo31U0Y/pBfZ01FpuC3qsfWWoyXEpurZbRZqzFynnHjJObj4GP/NFk?= =?us-ascii?Q?6sdom38Toda82Fh5kWuAX8NvpjwwCtPXdi4CC4JQRdHwR45MVMmhgpzAne2V?= =?us-ascii?Q?bKnHxvVOEDv/Y/RBTE/NDpluNECzchRmeSm6ksP6LtFWKN6j0SP+tkyApZx2?= =?us-ascii?Q?+e+SXbwn4Q=3D=3D?= X-OriginatorOrg: mt.com X-MS-Exchange-CrossTenant-Network-Message-Id: 05ce8d25-519e-470e-e133-08dede598497 X-MS-Exchange-CrossTenant-AuthSource: DB9PR03MB7180.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2026 08:01:59.3000 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: fb4c0aee-6cd2-482f-a1a5-717e7c02496b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ecXbngNDcL0nIKxB1Edrs1wyP/wSkSTnLTD8hsF9cQCMDW6kKuQx8afzbrpm8hVFq7E2VrvAewDx1z3Q26Fiqw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR03MB8839 On Thu, Jul 09, 2026 at 04:29:44PM +0300, Laurent Pinchart wrote: Hi Laurent, > On Thu, Jul 09, 2026 at 02:58:09PM +0200, Wojciech Dubowik wrote: > > From: Wojciech Dubowik > > > > The chip supports output lvds lanes in two orders, default <1 2 3 4> > > and <4 3 2 1>. Add parsing of an optional output lvds data-lanes > > property so we can inform chip that the lanes have been reversed. > > > > Signed-off-by: Wojciech Dubowik > > --- > > Changes in v2: > > - Parse existing data-lanes property instead of ading new DT > > bindings > > You still need to update the bindings to relax the ordering requirement > of the data-lanes property. The data-lanes have been defined for input nodes only. I will add an optinal binding for output nodes which are handled here. > > Does the device support less than 4 data lanes ? If not, the bindings > will also need to be updated to reflect that. There are 4 output lanes only, Regards, Wojtek > > > --- > > drivers/gpu/drm/bridge/ti-sn65dsi83.c | 50 +++++++++++++++++++++++++++ > > 1 file changed, 50 insertions(+) > > > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c > > index 42b451432bbb..4945d4c960c4 100644 > > --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c > > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c > > @@ -148,6 +148,18 @@ enum sn65dsi83_lvds_term { > > OHM_200 > > }; > > > > +enum { > > + NORMAL_LANE_MAPPING, > > + REVERSE_LANE_MAPPING, > > +}; > > + > > +#define DATA_LANES_COUNT 4 > > + > > +static const int supported_data_lane_mapping[][DATA_LANES_COUNT] = { > > + [NORMAL_LANE_MAPPING] = { 1, 2, 3, 4 }, > > + [REVERSE_LANE_MAPPING] = { 4, 3, 2, 1}, > > +}; > > + > > enum sn65dsi83_model { > > MODEL_SN65DSI83, > > MODEL_SN65DSI84, > > @@ -163,6 +175,7 @@ struct sn65dsi83 { > > struct regulator *vcc; > > bool lvds_dual_link; > > bool lvds_dual_link_even_odd_swap; > > + bool lvds_reverse_lanes_conf[2]; > > int lvds_vod_swing_conf[2]; > > int lvds_term_conf[2]; > > int irq; > > @@ -644,6 +657,10 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, > > regmap_write(ctx->regmap, REG_LVDS_LANE, > > (ctx->lvds_dual_link_even_odd_swap ? > > REG_LVDS_LANE_EVEN_ODD_SWAP : 0) | > > + (ctx->lvds_reverse_lanes_conf[CHANNEL_A] ? > > + REG_LVDS_LANE_CHA_REVERSE_LVDS : 0) | > > + (ctx->lvds_reverse_lanes_conf[CHANNEL_B] ? > > + REG_LVDS_LANE_CHB_REVERSE_LVDS : 0) | > > (ctx->lvds_term_conf[CHANNEL_A] ? > > REG_LVDS_LANE_CHA_LVDS_TERM : 0) | > > (ctx->lvds_term_conf[CHANNEL_B] ? > > @@ -832,10 +849,12 @@ static int sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 *ctx, int channel) > > u32 lvds_vod_swing_clk[2] = { 0, 1000000 }; > > /* Set default near end terminataion to 200 Ohm */ > > u32 lvds_term = 200; > > + u32 data_lanes[DATA_LANES_COUNT]; > > int lvds_vod_swing_conf; > > int ret = 0; > > int ret_data; > > int ret_clock; > > + int i, j; > > > > if (channel == CHANNEL_A) > > endpoint_reg = 2; > > @@ -854,6 +873,37 @@ static int sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 *ctx, int channel) > > goto exit; > > } > > > > + ret_data = of_property_read_u32_array(endpoint, "data-lanes", data_lanes, > > + ARRAY_SIZE(data_lanes)); > > + if (ret_data != 0 && ret_data != -EINVAL) { > > + ret = ret_data; > > + goto exit; > > + } > > + > > + if (!ret_data) { > > I wish we could drop this check, but as the data-lanes property is not > documented as mandatory, I suppose not all device trees use it :-( > > Could you, while at it, make the property mandatory in the bindings, to > ensure it gets specified in all future device trees (and fix in-tree > offenders, if any) ? > > > + for (i = 0; i < ARRAY_SIZE(supported_data_lane_mapping); i++) { > > + for (j = 0; j < DATA_LANES_COUNT; j++) { > > + if (data_lanes[j] != supported_data_lane_mapping[i][j]) > > + break; > > + } > > + > > + if (j == DATA_LANES_COUNT) > > + break; > > + } > > + > > + switch (i) { > > + case NORMAL_LANE_MAPPING: > > + break; > > + case REVERSE_LANE_MAPPING: > > + ctx->lvds_reverse_lanes_conf[channel] = true; > > + break; > > + default: > > + dev_err(dev, "invalid data lanes mapping\n"); > > + ret = -EINVAL; > > + goto exit; > > + } > > + } > > + > > ret_data = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-data-microvolt", > > lvds_vod_swing_data, ARRAY_SIZE(lvds_vod_swing_data)); > > if (ret_data != 0 && ret_data != -EINVAL) { > > -- > Regards, > > Laurent Pinchart