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Thu, 16 Jul 2026 08:30:46 +0000 Date: Thu, 16 Jul 2026 16:30:26 +0800 From: Chao Gao To: Paolo Bonzini , Sean Christopherson CC: , , Subject: Re: [PATCH v2 00/36] KVM: VMX APIC timer virtualization support Message-ID: References: Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: SI2PR01CA0021.apcprd01.prod.exchangelabs.com (2603:1096:4:192::19) To BN7PR11MB2836.namprd11.prod.outlook.com (2603:10b6:406:ad::26) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN7PR11MB2836:EE_|SJ0PR11MB7155:EE_ X-MS-Office365-Filtering-Correlation-Id: 7f157719-6587-43c5-9ce5-08dee31485f6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|23010399003|1800799024|376014|56012099006|10067099003|6133799003|11063799006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: EqmaWRVuFOMu24cejyQ6gdzZk+NXzSxItqfl/ejxAS+MWqWs+L9ZXt/CesHZWBkABgJ/ofSB5AtA13SYI0D+L78v3IKU/xMBXWgpMKBaTnq7TSBDLdieGyDZVuehDd94CXwtEzuTYbQutBpfgnGob4DUzhFDxprGz6HjsrB/Gl9XETA2YDXEkWfy3cZsPjpTlDxjGeTaXm6eb/He+pKJRI+S4IGzy8PJTiidpnhNkreEVl+pxBm0tnhKSA/5wxUld5mCZEHMBMKkcBqEpsjRjLT+gCafAtvSQlIUx0O+nJP7Oi637qkj1xnlg61gtPlYOvCtTiN/EuQC/wQ+StNv+n6GHTf7T2mHqIu9cC6J+newkNaBVhaRFQdlXN9RPSUDu2EkyNxXbNfBJxlsZEewH4HZeIOX+IUCP5FCK8vtcKUevTBpG9tdEy17TTansQqX360ZY6KTl0QmA4gzxCw0kw5ONPmqgBd0/DVRB4anhES1sPV7YpQFCdpC7PpDDdpoBX2K4nMY2OPF9rkDMG7AeajhWRVDJGbTwjmRUDahN9sdTVTqYfCGvR5eeh8/66/UsPv7heTZd3aX+K3JCyBha2Vir7eOQOB8fLmC1rNGbCawVsFqPxKJv2zu0bIpv2BfGs34Qk+798Rf73PD0K6VChCCtF+tHdDdwajqgEG5Y/U= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BN7PR11MB2836.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(23010399003)(1800799024)(376014)(56012099006)(10067099003)(6133799003)(11063799006)(22082099003)(18002099003);DIR:OUT;SFP:1101; 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Hi, I'm picking up the APIC timer virtualization work that Isaku posted [1]. While reviewing the series, I noticed that APIC timer virtualization and the VMX preemption timer share fundamental properties: - Both run only in guest mode, requiring KVM to switch to a software hrtimer when the vCPU blocks. - Both are armed/disarmed by writing a VMCS field (a countdown for the preemption timer, an absolute TSC deadline for APIC timer virtualization). These are exactly the properties the existing hv_timer infrastructure was designed for. This v2 series treats APIC timer virtualization as an entirely new mechanism, introducing a separate apic_virt_timer_in_use flag with five dedicated hooks and helpers to arm/disarm and manage state transitions in the common x86 flows (see [2]). I think we can avoid that. The idea is to reuse set_hv_timer()/cancel_hv_timer() for APIC timer virtualization, with two additions: First, the pieces specific to APIC timer virtualization: - Configure the timer interrupt vector in the VMCS. - Disable MSR interception for TSC_DEADLINE when the guest is in deadline mode (so writes go directly to hardware). - Re-enable interception when the guest leaves deadline mode or masks the timer. These are naturally scoped to LVTT register writes, so a single update_lvtt() vendor hook is sufficient. Second, tracking the timer state. With the preemption timer, KVM intercepts every MSR_IA32_TSC_DEADLINE write and knows precisely when a timer is armed. With APIC timer virtualization, the MSR is not intercepted and the guest arms and re-arms the timer without KVM's knowledge. When the vCPU halts, KVM needs to know whether a timer is armed and its deadline to set up the software wakeup timer. The solution is straightforward: on VM-exit, read back the deadline from the VMCS and update KVM's existing tracking (hv_timer_in_use and ktimer->tscdeadline). This is one vmcs_read64() per VM-exit, negligible compared to the exit cost itself. The existing vcpu_block() path then works unchanged. I prototyped this approach [3] for enabling APIC timer virtualization for L1 guests (nested support isn't considered). The result is roughly a third of the code (110 LoC vs. 300 LoC), with details of hypervisor timers (preemption timer or APIC timer virtualization) fully contained in VMX. The only change to common x86 code is a single kvm_x86_call in apic_update_lvtt(). I plan to post a series based on this approach and would appreciate feedback on the direction before doing so. Thanks, Chao [1] https://lore.kernel.org/kvm/cover.1772732517.git.isaku.yamahata@intel.com/ [2] https://lore.kernel.org/kvm/727502c8f79850fae6a8a476a624e5902861db39.1772732517.git.isaku.yamahata@intel.com/ [3] https://github.com/gaochaointel/linux-dev/commits/43056263022fe57cc9a10ebf2828f0f29611d6c