From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1034087AbcJ0Ofa (ORCPT ); Thu, 27 Oct 2016 10:35:30 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:43879 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S942639AbcJ0OfZ (ORCPT ); Thu, 27 Oct 2016 10:35:25 -0400 Date: Thu, 27 Oct 2016 16:32:30 +0200 (CEST) From: Thomas Gleixner To: Grzegorz Andrejczuk cc: mingo@redhat.com, "H. Peter Anvin" , x86@kernel.org, bp@suse.de, dave.hansen@linux.intel.com, lukasz.daniluk@intel.com, james.h.cownie@intel.com, "Pan, Jacob jun" , Piotr.Luc@intel.com, LKML Subject: Re: [PATCH v6: 1/4] x86/msr: Add R3MWAIT register and bit to msr-info.h In-Reply-To: <1477576923-3244-2-git-send-email-grzegorz.andrejczuk@intel.com> Message-ID: References: <1477576923-3244-1-git-send-email-grzegorz.andrejczuk@intel.com> <1477576923-3244-2-git-send-email-grzegorz.andrejczuk@intel.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 27 Oct 2016, Grzegorz Andrejczuk wrote: > Intel Xeon Phi x200 (codenamed Knights Landing) has MSR > MISC_THD_FEATURE_ENABLE 0x140. Oh well. I just reviewed another patch which names this register: MSR_MISC_FEATURE_ENABLES and that's how it's named in this document: http://www.intel.com/content/dam/www/public/us/en/documents/application-notes/virtualization-technology-flexmigration-application-note.pdf Can Intel please get its act together and document that register proper in the SDM? Thanks, tglx