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From: Thomas Gleixner <tglx@linutronix.de>
To: Vikas Shivappa <vikas.shivappa@linux.intel.com>
Cc: vikas.shivappa@intel.com, linux-kernel@vger.kernel.org,
	x86@kernel.org, hpa@zytor.com, mingo@kernel.org,
	peterz@infradead.org, ravi.v.shankar@intel.com,
	tony.luck@intel.com, fenghua.yu@intel.com, andi.kleen@intel.com
Subject: Re: [PATCH 7/8] x86/intel_rdt: schemata file support for MBA prepare\
Date: Wed, 1 Mar 2017 17:24:58 +0100 (CET)	[thread overview]
Message-ID: <alpine.DEB.2.20.1703011705360.4005@nanos> (raw)
In-Reply-To: <1487361535-9727-8-git-send-email-vikas.shivappa@linux.intel.com>

On Fri, 17 Feb 2017, Vikas Shivappa wrote:

Subject: x86/intel_rdt: schemata file support for MBA prepare

I have no idea what MBA prepare is. Is that yet another variant aside of
MBE?

> Add support to introduce generic APIs for control validation and writing
> QOS_MSRs for RDT resources. The control validation api is meant to
> validate the control values like cache bit mask for CAT and memory b/w
> percentage for MBA. A resource generic display format is also added and
> used for the resources depending on whether its displayed in
> hex/decimal.

The usual unpenetratable mess of random sentences lumped together.

> diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h
> index 24de64c..8748b0d 100644
> --- a/arch/x86/include/asm/intel_rdt.h
> +++ b/arch/x86/include/asm/intel_rdt.h
> @@ -77,6 +77,9 @@ struct rftype {
>   * @default_ctrl:		Specifies default cache cbm or mem b/w percent.
>   * @min_cbm_bits:		Minimum number of consecutive bits to be set
>   *				in a cache bit mask
> + * @format_str:		Per resource format string to show domain val

Can you please spell out words in comments instead of using random
abbreviations just as you see fit?

> + * @parse_ctrlval:		Per resource API to parse the ctrl values

That's not an API. That's a function pointer.

> + * @msr_update:		API to update QOS MSRs

Ditto.

>   * @info_files:		resctrl info files for the resource
>   * @infofiles_len:		Number of info files
>   * @max_delay:			Max throttle delay. Delay is the hardware
> @@ -105,6 +108,9 @@ struct rdt_resource {
>  	int			cbm_len;
>  	int			min_cbm_bits;
>  	u32			default_ctrl;
> +	const char		*format_str;
> +	int (*parse_ctrlval)	(char *buf, struct rdt_resource *r);
> +	void (*msr_update)	(void *a1, void *a2, struct rdt_resource *r);

void *a1, *a2? Dammit, both implementations (CAT and MBA) use the same
types. This just avoids type safety which does not magically come back by
your completely nonsensical typecasts inside the callback implementations.

> +void cqm_wrmsr(void *a1, void *a2, struct rdt_resource *r)

And this is global because it's only used in this file, right?

> +{
> +	struct rdt_domain *d = (struct rdt_domain *)a2;
> +	struct msr_param *m = (struct msr_param *)a1;

Oh well......

> +	int i;
> +
> +	for (i = m->low; i < m->high; i++) {
> +		int idx = cbm_idx(r, i);
> +
> +		wrmsrl(r->msr_base + idx, d->ctrl_val[i]);
> +	}
> +}

> -static bool cbm_validate(unsigned long var, struct rdt_resource *r)
> +static int cbm_validate(char *buf, unsigned long *data, struct rdt_resource *r)
>  {
> -	unsigned long first_bit, zero_bit;
> +	unsigned long first_bit, zero_bit, var;
> +	int ret;
> +
> +	ret = kstrtoul(buf, 16, &var);
> +	if (ret)
> +		return ret;
>  
>  	if (var == 0 || var > r->default_ctrl)
> -		return false;
> +		return -EINVAL;

So you change this function and the whole call chain to return either
-EINVAL or 0 instead of false/true.

And then you treat the integer return value as boolean on the call site
again:

> @@ -90,7 +95,7 @@ static int parse_line(char *line, struct rdt_resource *r)
>  		id = strsep(&dom, "=");
>  		if (kstrtoul(id, 10, &dom_id) || dom_id != d->id)
>  			return -EINVAL;
> -		if (parse_cbm(dom, r))
> +		if (r->parse_ctrlval(dom, r))
>  			return -EINVAL;

What's the purpose of this exercise? Annoying reviewers or what?

Thanks,

	tglx

  reply	other threads:[~2017-03-01 16:25 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-17 19:58 [PATCH 0/8 V2] x86/intel_rdt: Intel Memory bandwidth allocation Vikas Shivappa
2017-02-17 19:58 ` [PATCH 1/8] Documentation, x86: Documentation for Intel Mem b/w allocation Vikas Shivappa
2017-02-17 19:58 ` [PATCH 2/8] x86/intel_rdt/mba: Generalize the naming to get ready for MBA Vikas Shivappa
2017-02-17 19:58 ` [PATCH 3/8] x86/intel_rdt/mba: Memory b/w allocation feature detect Vikas Shivappa
2017-02-17 19:58 ` [PATCH 4/8] x86/intel_rct/mba: Add MBA structures and initialize MBA Vikas Shivappa
2017-03-01 15:24   ` Thomas Gleixner
2017-03-10 21:51     ` Shivappa Vikas
2017-02-17 19:58 ` [PATCH 5/8] x86/intel_rdt: info file support for MBA prepare Vikas Shivappa
2017-03-01 15:34   ` Thomas Gleixner
2017-03-10 22:04     ` Shivappa Vikas
2017-02-17 19:58 ` [PATCH 6/8] x86/intel_rdt/mba: Add info directory files for MBA Vikas Shivappa
2017-03-01 16:05   ` Thomas Gleixner
2017-03-10 23:26     ` Shivappa Vikas
2017-02-17 19:58 ` [PATCH 7/8] x86/intel_rdt: schemata file support for MBA prepare Vikas Shivappa
2017-03-01 16:24   ` Thomas Gleixner [this message]
2017-03-30 19:05     ` [PATCH 7/8] x86/intel_rdt: schemata file support for MBA prepare\ Shivappa Vikas
2017-02-17 19:58 ` [PATCH 8/8] x86/intel_rdt/mba: Add schemata file support for MBA Vikas Shivappa
2017-03-01 16:59   ` Thomas Gleixner

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