From mboxrd@z Thu Jan  1 00:00:00 1970
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1754096AbeAJLGL (ORCPT <rfc822;ralf@linux-mips.org> + 1 other);
        Wed, 10 Jan 2018 06:06:11 -0500
Received: from Galois.linutronix.de ([146.0.238.70]:55344 "EHLO
        Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1752031AbeAJLGJ (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Wed, 10 Jan 2018 06:06:09 -0500
Date: Wed, 10 Jan 2018 12:06:06 +0100 (CET)
From: Thomas Gleixner <tglx@linutronix.de>
To: Ingo Molnar <mingo@kernel.org>
cc: LKML <linux-kernel@vger.kernel.org>,
        Linus Torvalds <torvalds@linuxfoundation.org>, x86@kernel.org,
        Peter Zijlstra <peterz@infradead.org>,
        Borislav Petkov <bp@alien8.de>,
        David Woodhouse <dwmw@amazon.co.uk>,
        Tim Chen <tim.c.chen@linux.intel.com>,
        Andrea Arcangeli <aarcange@redhat.com>,
        Andi Kleen <ak@linux.intel.com>,
        Greg KH <gregkh@linuxfoundation.org>,
        Dave Hansen <dave.hansen@intel.com>,
        Andy Lutomirski <luto@kernel.org>,
        Arjan Van De Ven <arjan.van.de.ven@intel.com>,
        Linus Torvalds <torvalds@linux-foundation.org>
Subject: Re: [patch RFC 4/5] x86/cpufeatures: Detect Speculation control
 feature
In-Reply-To: <20180110063211.z6w55gwxm5szmt2l@gmail.com>
Message-ID: <alpine.DEB.2.20.1801101204250.1919@nanos>
References: <20180110010652.404145126@linutronix.de> <20180110011350.759392067@linutronix.de> <20180110063211.z6w55gwxm5szmt2l@gmail.com>
User-Agent: Alpine 2.20 (DEB 67 2015-01-07)
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
Return-Path: <linux-kernel-owner@vger.kernel.org>

On Wed, 10 Jan 2018, Ingo Molnar wrote:
> > If CPUID(7).RDX[26] is set then MSR_IA32_SPEC_CTRL (0x48) is available and
> > bit 0 of that MSR controls whether Indirect Branch Speculation is
> > restricted or not. The control bit is named IBRS (Indirect Branch
> > Restricted Speculation). The IBSR bit can be unconditionally set to 1
> > without clearing it before.
> 
> Argh for inverted logic: why was the control bit defined for a _negated_ value, 
> i.e. why does '0' mean "don't don't speculate"?
> 
> And yes, I know what's behind it: this way 'IBRS' can be called a 'mitigation 
> feature' that can be 'enabled', instead of calling it a 'broken CPU feature 
> feature' that has to be disabled ...
> 
> That's nonsense that causes confusion to no end:

Yes, it's horrible and on my todo list to clean that up at least on any
layer which is above the pure MSR definition level, which we can't change.

The steam blasting of that mess is not even halfways done.

Thanks,

	tglx