Re: Q: smp.c && barriers (Was: [PATCH 1/4] generic-smp: remove single ipi fallback for smp_call_function_many())

Benjamin Herrenschmidt
2009-02-19T06:49:21Z

> It might hide some architecture-specific implementation issue, of course,
> so random amounts of "smp_mb()"s sprinkled around might well make some
> architecture "work", but it's in no way guaranteed. A smp_mb() does not
> guarantee that some separate IPI network is ordered - that may well take
> some random machine-specific IO cycle.
>
> That said, at least on x86, taking an interrupt should be a serializing
> event, so there should be no reason for anything on the receiving side.
> The _sending_ side might need to make sure that there is serialization
> when generating the IPI (so that the IPI cannot happen while the writes
> are still in some per-CPU write buffer and haven't become part of the
> cache coherency domain).
>
> And at least on x86 it's actually pretty hard to generate out-of-order
> accesses to begin with (_regardless_ of any issues external to the CPU).
> You have to work at it, and use a WC memory area, and I'm pretty sure we
> use UC for the apic accesses.

On powerpc, I suspect an smp_mb() on the sender would be useful... it
mostly depends how the IPI is generated but in most case it's going to
be an MMIO write, ie non-cached write which isn't ordered vs. any
previous cached store except using a full sync (which is what smp_mb()
does).

Cheers,
Ben.