Re: [PATCH v2 2/4] usb: xhci: Honor PORTSC.TM if valid

[Thinh Nguyen <Thinh.Nguyen@synopsys.com>]

On Wed, Jul 15, 2026, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Currently, the only way for the USB core to determine whether the link
> is native or tunneled is via an Intel vendor-specific Extended
> Capability.
> 
> The XHCI specification v1.2 and newer expose a common ext_cap,
> indicating whether BIT(2) of PORTSC can be interpreted as the tunneling
> status.
> 
> Make use of that and fall back to the existing Intel-specific path if
> the ext_cap is absent.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
>  drivers/usb/host/xhci-ext-caps.h |  3 +++
>  drivers/usb/host/xhci-hub.c      | 19 ++++++++++++++++---
>  drivers/usb/host/xhci-port.h     |  3 ++-
>  3 files changed, 21 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h
> index 22e53a750e2a..af7d624cd38e 100644
> --- a/drivers/usb/host/xhci-ext-caps.h
> +++ b/drivers/usb/host/xhci-ext-caps.h
> @@ -66,6 +66,9 @@
>  #define XHCI_HLC               (1 << 19)
>  #define XHCI_BLC               (1 << 20)
>  
> +/* USB3 tunneling support capability - section 7.11 */
> +#define XHCI_USB3_TUNNELING_SUPPORTED	BIT(16)
> +
>  /* Intel SPR shadow capability */
>  #define XHCI_INTEL_SPR_ESS_PORT_OFFSET  0x8ac4	/* SuperSpeed port control */
>  #define XHCI_INTEL_SPR_TUNEN	BIT(4)		/* Tunnel mode enabled */
> diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
> index b0264bd8577a..402e98ab95ee 100644
> --- a/drivers/usb/host/xhci-hub.c
> +++ b/drivers/usb/host/xhci-hub.c
> @@ -766,17 +766,30 @@ static int xhci_exit_test_mode(struct xhci_hcd *xhci)
>  enum usb_link_tunnel_mode xhci_port_is_tunneled(struct xhci_hcd *xhci,
>  						struct xhci_port *port)
>  {
> +	void __iomem *base = &xhci->cap_regs->hc_capbase;
>  	struct usb_hcd *hcd;
> -	void __iomem *base;
>  	u32 offset;
> +	u32 val;

Continue from the response on [PATCH v2 3/4], base on the priority to
determine the tunnel_mode:

First we should check if tunnel_mode_override is set:

	if (xhci->tunnel_mode_override && xhci->tunnel_mode) {
		enum usb_link_tunnel_mode mode;

		mode = xhci->tunnel_mode(xhci_to_hcd(xhci), port->hcd_portnum);
		if (mode != USB_LINK_UNKNOWN)
			return mode;
	}

>  
> -	/* Don't try and probe this capability for non-Intel hosts */
> +	/* Prefer the XHCI v1.2 ext_cap if advertised */
> +	offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_USB3_TUNNELING);
> +	if (offset) {
> +		if (!(readl(base + offset) & XHCI_USB3_TUNNELING_SUPPORTED))
> +			return USB_LINK_NATIVE;

Second, don't return early here. Check if XHCI_EXT_CAPS_USB3_TUNNELING
present and supported:

	if (offset && (readl(base + offset) & XHCI_USB3_TUNNELING_SUPPORTED)) {

> +
> +		val = xhci_portsc_readl(port);
> +		if (val & PORT_TM)
> +			return USB_LINK_TUNNELED;
> +
> +		return USB_LINK_NATIVE;
> +	}
> +

Third, check for Intel PCI and keep it as is here:

> +	/* Fall back to the legacy Intel-specific ext_cap */
>  	hcd = xhci_to_hcd(xhci);
>  	if (!dev_is_pci(hcd->self.controller) ||
>  	    to_pci_dev(hcd->self.controller)->vendor != PCI_VENDOR_ID_INTEL)
>  		return USB_LINK_UNKNOWN;
>  
> -	base = &xhci->cap_regs->hc_capbase;
>  	offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_INTEL_SPR_SHADOW);
>  
>  	if (offset && offset <= XHCI_INTEL_SPR_ESS_PORT_OFFSET) {
> diff --git a/drivers/usb/host/xhci-port.h b/drivers/usb/host/xhci-port.h
> index 889b5fb0fcd8..215c9cadbc34 100644
> --- a/drivers/usb/host/xhci-port.h
> +++ b/drivers/usb/host/xhci-port.h
> @@ -5,7 +5,8 @@
>  #define PORT_CONNECT	(1 << 0)
>  /* true: port enabled */
>  #define PORT_PE		(1 << 1)
> -/* bit 2 reserved and zeroed */
> +/* true: port is tunneling traffic over USB4 */
> +#define PORT_TM		(1 << 2)
>  /* true: port has an over-current condition */
>  #define PORT_OC		(1 << 3)
>  /* true: port reset signaling asserted */
> 
> -- 
> 2.55.0
> 

Thanks,
Thinh