From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 02D3D43F8C4 for ; Tue, 28 Jul 2026 14:06:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785247612; cv=none; b=bYda9GHLPEOZOcqsufz90XomKC1aLx70ZGhFiqS1cbv/O8cEhc35UlPc8j86Cz4Y8pBbykc8ulswPIYwNyE+VlQJJAjpJ5Il5Vr85CKIyv3hB4it2dP362DYj7B1i+iACYF5Bgi9i5poxxYlLy2nWrr7v3SfQY6HHCOJm+ey1r4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785247612; c=relaxed/simple; bh=oh/tz0oaXwZk1r+xJ7nKsqhdVTLA4/q103YvNyJqQlk=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=uFQ5geMOf/n9uTnU+/LEqz2MwrDZqWTLmT3hR2zvMB/jjk/vOWlbyc7VsxaJG5Nsb3T141X5libWgJf4HKkJOvfPuCEdVYGJ/g5G7QuhVEKrp0uBIBALt6NpgE9s7ARKt0hpAOQhZonvEScKvo1elftQGVk05omVtXWqY8crC/0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=nEgnPrQn; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="nEgnPrQn" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 499771650 for ; Tue, 28 Jul 2026 07:06:46 -0700 (PDT) Received: from [10.2.11.34] (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2ABC63F66F for ; Tue, 28 Jul 2026 07:06:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1785247610; bh=oh/tz0oaXwZk1r+xJ7nKsqhdVTLA4/q103YvNyJqQlk=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=nEgnPrQnddJj0XZcAQSP5Hzzfq96edbEW5H5vvfeTvVEskkO9EclAUhm96Fzpmknb 221hEFg2pKTjH3tMj1q9++RwlQIFdCuq5Ffy06xyQ9OrQ8zrIW0eGrfYN0YU9pjK+9 vlm8Hr02L1y2mef2seQnCI06YBdANJNXVndggIUg= Date: Tue, 28 Jul 2026 15:06:47 +0100 From: Liviu Dudau To: Raveendra Talabattula Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, james.qian.wang@arm.com, vincenzo.frascino@arm.com, nayden.kanchev@arm.com, charvi.mehta@arm.com, Asad Malik Subject: Re: [PATCH 1/2] drm/komeda: Fix bits parsing of GLB_CORE_ID Message-ID: References: <20260721135227.439413-1-raveendra.talabattula@arm.com> <20260721135227.439413-2-raveendra.talabattula@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260721135227.439413-2-raveendra.talabattula@arm.com> On Tue, Jul 21, 2026 at 02:52:26PM +0100, Raveendra Talabattula wrote: > GLB_CORE_ID contains the product and version information returned by the > hardware. The current macros parses VERSION_MINOR as a 4-bit field and > VERSION_STATUS as an 8-bit field, which does not match the register > layout. As a result, the driver reports an incorrect version number. > > Fix the parsing macros to match the hardware specification: > - VERSION_MINOR is 8 bits at [11:4] > - VERSION_STATUS is 4 bits at [3:0] > > Fixes: bd628c1bed79 ("drm/komeda: komeda_dev/pipeline/component definition and initialzation") > Signed-off-by: Asad Malik > Signed-off-by: Raveendra Talabattula > --- > drivers/gpu/drm/arm/display/include/malidp_product.h | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/arm/display/include/malidp_product.h b/drivers/gpu/drm/arm/display/include/malidp_product.h > index 6f954bcdf40e..bf63c4e05c3e 100644 > --- a/drivers/gpu/drm/arm/display/include/malidp_product.h > +++ b/drivers/gpu/drm/arm/display/include/malidp_product.h > @@ -8,14 +8,18 @@ > #define _MALIDP_PRODUCT_H_ > > /* Product identification */ > +/* GLB_CORE_ID fields as per HW specification: > + * MINOR is 8 bits ([11:4]) and STATUS is 4 bits ([3:0]). > + * Update masks/shifts accordingly. > + */ > #define MALIDP_CORE_ID(__product, __major, __minor, __status) \ > ((((__product) & 0xFFFF) << 16) | (((__major) & 0xF) << 12) | \ > - (((__minor) & 0xF) << 8) | ((__status) & 0xFF)) > + (((__minor) & 0xFF) << 4) | ((__status) & 0xF)) > > -#define MALIDP_CORE_ID_PRODUCT_ID(__core_id) ((__u32)(__core_id) >> 16) > +#define MALIDP_CORE_ID_PRODUCT_ID(__core_id) (((__u32)(__core_id) >> 16) & 0xFFFF) This change is redundant. > #define MALIDP_CORE_ID_MAJOR(__core_id) (((__u32)(__core_id) >> 12) & 0xF) > -#define MALIDP_CORE_ID_MINOR(__core_id) (((__u32)(__core_id) >> 8) & 0xF) > -#define MALIDP_CORE_ID_STATUS(__core_id) (((__u32)(__core_id)) & 0xFF) > +#define MALIDP_CORE_ID_MINOR(__core_id) (((__u32)(__core_id) >> 4) & 0xFF) > +#define MALIDP_CORE_ID_STATUS(__core_id) (((__u32)(__core_id) >> 0) & 0xF) Shift by zero is unnecessary. Simple bitwise AND is enough. Reviewed-by: Liviu Dudau Best regards, Liviu > > /* Mali-display product IDs */ > #define MALIDP_D71_PRODUCT_ID 0x0071 > -- > 2.43.0 > -- ==================== | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --------------- ¯\_(ツ)_/¯