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Wed, 29 Jul 2026 01:34:51 +0000 Date: Wed, 29 Jul 2026 09:34:40 +0800 From: Chao Gao To: Paolo Bonzini , Sean Christopherson , CC: , , Subject: Re: [PATCH v2 00/36] KVM: VMX APIC timer virtualization support Message-ID: References: Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: SI2PR02CA0017.apcprd02.prod.outlook.com (2603:1096:4:194::17) To BY5PR11MB4450.namprd11.prod.outlook.com (2603:10b6:a03:1be::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY5PR11MB4450:EE_|DM3PPFD320E2257:EE_ X-MS-Office365-Filtering-Correlation-Id: 705defc6-61d1-4dd7-f6b1-08deed119444 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|366016|376014|11063799006|56012099006|4143699003|10067099003|6133799003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: 4sdnft7OLcian//D1fcjpBSjFcb9BnLHdnrMJ2fUKb4kg6BsAl4Y5EelE5v//glsnh+OBNbZZJ8hSokUiSoAnJKL31NDFW6XIXtjajZaNp6eDm3qqs8+9/Kbrtn2ze0tW9SKaKMh691ZfkJNjPuLuuQDvygFII989Bb1qne+ZgWjhD0+GLwiV99NDb/e5RvjkRxeleXh1qr1Hg8t0mK1y0lw5dvqV2WDoh3X+HTDWJ6ursFkpz55roDvbnAIV3WDWvoTdaoseOuFC6TwZBNswNMUNhsTyt09CHveDk3FM88CLXKQ4ybbwwzzf1uOUPPSt8cyNCDrKrLVv5rLaDjQMA4dCNOXQnsKjqRN56cLFVfI8VPza51rDziIPmG5Ip3/jdqMGAB7Q+3Wze+OpEO5M5UDI/Q1wqOeOsAdAo+XzkmkK1DG4gscf7OOra1dlM3KjeuhtD6XNGb3n4G4zwCdp4kBovgBRqAuR7Uhy5LSp/mvvuPRufEMS3eYuZop15+chCZTU3CXoPobQTzDozU7a6a1EcRhroRh8RP7yImu9HPNUuXoyhlCKOvFOdfGpMnSF+1trtDH8MwC4vh8px6S28Y7wQitAf8broCaETwzGEsupoh1we1+4KmHrr5j/osF X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BY5PR11MB4450.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(23010399003)(366016)(376014)(11063799006)(56012099006)(4143699003)(10067099003)(6133799003)(22082099003)(18002099003);DIR:OUT;SFP:1101; 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On Thu, Jul 16, 2026 at 04:30:57PM +0800, Chao Gao wrote: >On Thu, Mar 05, 2026 at 09:43:40AM -0800, isaku.yamahata@intel.com wrote: >>From: Isaku Yamahata >> >>This patch series is v2 of VMX APIC timer virtualization support. > >Hi, > >I'm picking up the APIC timer virtualization work that Isaku posted [1]. >While reviewing the series, I noticed that APIC timer virtualization and >the VMX preemption timer share fundamental properties: > > - Both run only in guest mode, requiring KVM to switch to a software > hrtimer when the vCPU blocks. > - Both are armed/disarmed by writing a VMCS field (a countdown for the > preemption timer, an absolute TSC deadline for APIC timer > virtualization). > >These are exactly the properties the existing hv_timer infrastructure >was designed for. This v2 series treats APIC timer virtualization as >an entirely new mechanism, introducing a separate apic_virt_timer_in_use >flag with five dedicated hooks and helpers to arm/disarm and manage state >transitions in the common x86 flows (see [2]). I think we can avoid that. > >The idea is to reuse set_hv_timer()/cancel_hv_timer() for APIC timer >virtualization, with two additions: > >First, the pieces specific to APIC timer virtualization: > > - Configure the timer interrupt vector in the VMCS. > - Disable MSR interception for TSC_DEADLINE when the guest is in > deadline mode (so writes go directly to hardware). > - Re-enable interception when the guest leaves deadline mode or masks > the timer. > >These are naturally scoped to LVTT register writes, so a single >update_lvtt() vendor hook is sufficient. > >Second, tracking the timer state. With the preemption timer, KVM >intercepts every MSR_IA32_TSC_DEADLINE write and knows precisely when a >timer is armed. With APIC timer virtualization, the MSR is not >intercepted and the guest arms and re-arms the timer without KVM's >knowledge. When the vCPU halts, KVM needs to know whether a timer is >armed and its deadline to set up the software wakeup timer. > >The solution is straightforward: on VM-exit, read back the deadline from >the VMCS and update KVM's existing tracking (hv_timer_in_use and >ktimer->tscdeadline). This is one vmcs_read64() per VM-exit, negligible >compared to the exit cost itself. The existing vcpu_block() path then >works unchanged. > >I prototyped this approach [3] for enabling APIC timer virtualization for >L1 guests (nested support isn't considered). The result is roughly a third >of the code (110 LoC vs. 300 LoC), with details of hypervisor timers >(preemption timer or APIC timer virtualization) fully contained in VMX. The >only change to common x86 code is a single kvm_x86_call in apic_update_lvtt(). > >I plan to post a series based on this approach and would appreciate >feedback on the direction before doing so. > >Thanks, >Chao > >[1] https://lore.kernel.org/kvm/cover.1772732517.git.isaku.yamahata@intel.com/ >[2] https://lore.kernel.org/kvm/727502c8f79850fae6a8a476a624e5902861db39.1772732517.git.isaku.yamahata@intel.com/ >[3] https://github.com/gaochaointel/linux-dev/commits/43056263022fe57cc9a10ebf2828f0f29611d6c