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[73.183.53.213]) by smtp.gmail.com with ESMTPSA id 00721157ae682-81fccf9555dsm57109317b3.20.2026.08.03.07.39.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:39:21 -0700 (PDT) Date: Mon, 3 Aug 2026 10:39:19 -0400 From: Brian Masney To: Louis-Alexis Eyraud Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Philipp Zabel , Edward-JW Yang , Richard Cochran , Chen-Yu Tsai , kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org Subject: Re: [PATCH v5 11/25] clk: mediatek: pll: Factorise pll power on/off sequences Message-ID: References: <20260801-mt8189-clocks-system-base-v5-0-ac4410697cc2@collabora.com> <20260801-mt8189-clocks-system-base-v5-11-ac4410697cc2@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260801-mt8189-clocks-system-base-v5-11-ac4410697cc2@collabora.com> User-Agent: Mutt/2.4.0 (2026-06-19) On Sat, Aug 01, 2026 at 01:20:57PM +0200, Louis-Alexis Eyraud wrote: > In order to prepare the MT8189 SoC support, that requires different > registers to control PLL status and perform reset BAR, and so a > different sets of clock operations, split the pll power on and off > sequences from mtk_pll_prepare/unprepare functions into private > subfunctions. > > Signed-off-by: Louis-Alexis Eyraud Reviewed-by: Brian Masney