From: Brian Masney <bmasney@redhat.com>
To: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Chun-Jie Chen <chun-jie.chen@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Edward-JW Yang <edward-jw.yang@mediatek.com>,
Richard Cochran <richardcochran@gmail.com>,
Chen-Yu Tsai <wenst@chromium.org>,
kernel@collabora.com, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, netdev@vger.kernel.org
Subject: Re: [PATCH v5 15/25] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs
Date: Mon, 3 Aug 2026 10:46:21 -0400 [thread overview]
Message-ID: <anCpvYJJf2FChBHE@redhat.com> (raw)
In-Reply-To: <20260801-mt8189-clocks-system-base-v5-15-ac4410697cc2@collabora.com>
On Sat, Aug 01, 2026 at 01:21:01PM +0200, Louis-Alexis Eyraud wrote:
> Add new set of PLL FHCTL clock operations, that uses the new prepare
> and unprepare methods, added in PLL for MT8189 SoC to support this
> logic.
>
> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
next prev parent reply other threads:[~2026-08-03 14:46 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-01 11:20 [PATCH v5 00/25] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 01/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186 Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 02/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8192 Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 03/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8195 Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 04/25] dt-bindings: clock: mediatek: reorder MT8186 compatibles Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 05/25] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 06/25] dt-bindings: clock: mediatek: regroup MT8192 " Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 07/25] dt-bindings: clock: mediatek: regroup MT8195 " Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 08/25] dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 09/25] clk: mediatek: Harmonize mtk_pll_fenc related symbol names Louis-Alexis Eyraud
2026-08-03 14:32 ` Brian Masney
2026-08-01 11:20 ` [PATCH v5 10/25] clk: mediatek: pll: Add BAR reset register offsets Louis-Alexis Eyraud
2026-08-03 14:37 ` Brian Masney
2026-08-01 11:20 ` [PATCH v5 11/25] clk: mediatek: pll: Factorise pll power on/off sequences Louis-Alexis Eyraud
2026-08-03 14:39 ` Brian Masney
2026-08-01 11:20 ` [PATCH v5 12/25] clk: mediatek: pll: Add PLL stabilization delay definition Louis-Alexis Eyraud
2026-08-03 14:40 ` Brian Masney
2026-08-01 11:20 ` [PATCH v5 13/25] clk: mediatek: pll: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-08-03 14:44 ` Brian Masney
2026-08-01 11:21 ` [PATCH v5 14/25] clk: mediatek: pllfh: Add configurable clock ops to mtk_pllfh_data Louis-Alexis Eyraud
2026-08-03 14:45 ` Brian Masney
2026-08-01 11:21 ` [PATCH v5 15/25] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-08-03 14:46 ` Brian Masney [this message]
2026-08-01 11:21 ` [PATCH v5 16/25] clk: mediatek: Add MT8189 apmixedsys clock support Louis-Alexis Eyraud
2026-08-03 15:12 ` Brian Masney
2026-08-01 11:21 ` [PATCH v5 17/25] clk: mediatek: Add MT8189 topckgen " Louis-Alexis Eyraud
2026-08-03 15:16 ` Brian Masney
2026-08-01 11:21 ` [PATCH v5 18/25] clk: mediatek: Add MT8189 vlpckgen " Louis-Alexis Eyraud
2026-08-03 15:17 ` Brian Masney
2026-08-01 11:21 ` [PATCH v5 19/25] clk: mediatek: Add MT8189 vlpcfg " Louis-Alexis Eyraud
2026-08-03 15:19 ` Brian Masney
2026-08-01 11:21 ` [PATCH v5 20/25] clk: mediatek: Add MT8189 bus " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 21/25] clk: mediatek: Add MT8189 dbgao " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 22/25] clk: mediatek: Add MT8189 dvfsrc " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 23/25] clk: mediatek: Add MT8189 i2c " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 24/25] clk: mediatek: Add MT8189 scp " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 25/25] clk: mediatek: Add MT8189 ufs " Louis-Alexis Eyraud
2026-08-03 15:23 ` [PATCH v5 00/25] MT8189: Add support for system and base clock controllers Brian Masney
2026-08-03 19:51 ` Jakub Kicinski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=anCpvYJJf2FChBHE@redhat.com \
--to=bmasney@redhat.com \
--cc=angelogioacchino.delregno@collabora.com \
--cc=chun-jie.chen@mediatek.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=edward-jw.yang@mediatek.com \
--cc=kernel@collabora.com \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=louisalexis.eyraud@collabora.com \
--cc=matthias.bgg@gmail.com \
--cc=mturquette@baylibre.com \
--cc=netdev@vger.kernel.org \
--cc=p.zabel@pengutronix.de \
--cc=richardcochran@gmail.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=wenst@chromium.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).