From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6124B3BBA05 for ; Tue, 4 Aug 2026 17:55:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785866150; cv=none; b=FfAxC6NU/dOTXr36DkjZPQrVVvrKJW4LenCSYEES32RqBi+6d4+P0SOpQ3A1qige8Ncx9vPqS27+xMotfikHyo6HzTzV01oKbVoXEZdJAEAf4NCh1QM7Y7CLirDLrg0YHShghd623Riaa/hHy05ojyYPNIVqlnqIkOilKPu5uUQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785866150; c=relaxed/simple; bh=SmK/arxqD2goLNyBvHw5V+NpwaO4Xqn3fhYGtQRIlC0=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=r5SRLol6tkY4M16YdcJBw4vii9BNrag7GegwbhmDLyQSBpIb4gjRcaDyP01sAeedSg0rH1vWbQuMM5swDSVenfbj3I/aw0P77t4zMxwTg/ywv2o25bGqYZGfCShfmi/IJJywSqmD1aYboi2ozGKXGB3Sv8ByOaEJvNHDc5vGRhA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TZa48Rt4; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TZa48Rt4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 67C611F000E9; Tue, 4 Aug 2026 17:55:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785866149; bh=zaQDBaPiTpiGSK2h7eyvcfOitjrDidR7aYYXWYrAlAc=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=TZa48Rt44WW9RFBAvzkMaT7BtlQJLmBKtZHGEGWpfcMTRwF24pkgsPEXhiqd1TN0D ZV5h+tlTh1gxvSQ7SkHQItMJadiQJ9GxOZtMD51lLWcjXjS3Erl6iEaIUC+IjHIwxb K421j63Mg950mL7L/XqwK6sO2plQlWqxvApN8Lg9FKuJr0+xoAVZqawLVRKp/7fkls e1qUydGoBEeRyorjKExmtt0kgQCEXEYBUqpQvb3F6XLyyqft8QqyPNH+7XH7qK64lN FoufeoeaohN1yTbrhjMNrtTUZRoHHoiCNREVgKqeGRBgkwY9MEpLND9UWho8Ld45ux j7jFfwFPWOLJQ== Date: Tue, 4 Aug 2026 19:55:45 +0200 From: Ingo Molnar To: Guo Chaohong Cc: Peter Zijlstra , tim.c.chen@linux.intel.com, bp@alien8.de, x86@kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] x86/cpu/hygon: Introduce macros for hygon family numbers Message-ID: References: <20260803051248.3684453-1-guochaohong@open-hieco.net> <20260803061022.GS49951@noisy.programming.kicks-ass.net> <21e9fad3-68f8-4560-8e04-25085e6531be@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <21e9fad3-68f8-4560-8e04-25085e6531be@open-hieco.net> * Guo Chaohong wrote: > > On 8/3/2026 2:10 PM, Peter Zijlstra wrote: > > On Mon, Aug 03, 2026 at 01:12:47PM +0800, Chaohong Guo wrote: > > > Consolidate all magic numbers of hygon CPUs into a header file, > > > The macros describe the family/model numbers of hygon CPUs. > > > > > > Signed-off-by: Chaohong Guo > > > Co-developed-by: Zhiquan Li > > > Signed-off-by: Zhiquan Li > > > --- > > > arch/x86/include/asm/cpu_device_id.h | 2 ++ > > > arch/x86/include/asm/processor-hygon.h | 20 ++++++++++++++++++++ > > > 2 files changed, 22 insertions(+) > > > create mode 100644 arch/x86/include/asm/processor-hygon.h > > > > > > diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cpu_device_id.h > > > index c62d8fae52c3..447837d15f87 100644 > > > --- a/arch/x86/include/asm/cpu_device_id.h > > > +++ b/arch/x86/include/asm/cpu_device_id.h > > > @@ -44,6 +44,8 @@ > > > #include > > > /* And the X86_VENDOR_* ones */ > > > #include > > > +/* Hygon HFM model defines */ > > > +#include > > I'll take these, but Boris, should I rename this to hygon-family.h to > > match intel-family.h ? > > > I will rename it to hygon-family.h, fix the SOB order as Boris suggested, > and then send it out. Please also: - Fix the 7447V model confusion problem I mentioned, - and take a good look at canonical header guard definition placement in existing x86 headers and use that format, not the random placement your patch introduces ... Thanks, Ingo