From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E41283C5826 for ; Wed, 5 Aug 2026 09:21:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785921664; cv=none; b=BE9AO5qMEEklkLwoeuXf9uMVLRYOqel9rCmCGi4IKFud0kQhxgjGFYRg6HfvseJDzKNoQRRdrfGmUllbF2Z6b28O/N1JhGLcrvJRxNzTQcsamzhVhh43U3HiO41LPgnt1SR3a5Ojyij8YdiXyJegmbgPK92NHlKSz+xrjaZ8tKY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785921664; c=relaxed/simple; bh=LW9EZgLM/owzJSlQ+NzI5vnyZ9lEG0L/Js2ah2Km9MQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=GRp2XpnJoV3lhjl6t8aBoVrLXtGFOxyW+FsBXFsOMQn1VyuZO4GPhgQebubMxkLmCxEcgmqr7N+uQjUkY0U8XC1h0wL03hPenIpBMumzATb+wvOjDp5eCrdLNy8Ar4LuXuS2ZNvAbwPN1/ZhlWgdheZ9vtT43D15lcWi4IdU3Ts= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=iZT3KwBE; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="iZT3KwBE" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C11A9153B; Wed, 5 Aug 2026 02:20:54 -0700 (PDT) Received: from localhost (a079125.arm.com [10.164.21.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1545E3F66F; Wed, 5 Aug 2026 02:20:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1785921658; bh=LW9EZgLM/owzJSlQ+NzI5vnyZ9lEG0L/Js2ah2Km9MQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=iZT3KwBEAB9OYz13EITRYb/2Da5rPA80Mbw8sMzATWs41jEERnPrdboNZth/UUT3B lt7OE3Gxz64bJLGuOiSnQUXV51OeOGgZZBxg/5frtN39aKC+Uk33lfd2us+HA96vIy ybXM0x18k9qEkKRIomc0dM0G41zjeb9aeh2xiGu4= Date: Wed, 5 Aug 2026 14:50:55 +0530 From: Linu Cherian To: Will Deacon Cc: Catalin Marinas , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Gavin Shan Subject: Re: [PATCH v4 6/6] arm64: cpufeature: Detect BBML3 based on ID_AA64MMFR2_EL1.BBM Message-ID: References: <20260723044034.2983651-1-linu.cherian@arm.com> <20260723044034.2983651-7-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Hi, On Tue, Aug 04, 2026 at 02:51:28PM +0100, Will Deacon wrote: > On Mon, Aug 03, 2026 at 09:22:02AM +0530, Linu Cherian wrote: > > Hi Will, > > > > On Fri, Jul 31, 2026 at 04:13:20PM +0100, Will Deacon wrote: > > > On Thu, Jul 23, 2026 at 10:10:33AM +0530, Linu Cherian wrote: > > > > Add ID_AA64MMFR2_EL1.BBM based BBML3 feature detection in > > > > cpu_supports_bbml3() so that cpus with the feature would > > > > not have to be added into MIDR based supports_bbml3_list. > > > > > > > > Reviewed-by: Gavin Shan > > > > Reviewed-by: Anshuman Khandual > > > > Signed-off-by: Linu Cherian > > > > --- > > > > arch/arm64/kernel/cpufeature.c | 17 +++++++++-------- > > > > 1 file changed, 9 insertions(+), 8 deletions(-) > > > > > > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > > > index 896bafdb00b1..dbd7d187520c 100644 > > > > --- a/arch/arm64/kernel/cpufeature.c > > > > +++ b/arch/arm64/kernel/cpufeature.c > > > > @@ -2133,6 +2133,12 @@ static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, > > > > > > > > bool cpu_supports_bbml3(void) > > > > { > > > > + u64 mmfr2; > > > > + > > > > + mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1); > > > > + if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) >= ID_AA64MMFR2_EL1_BBM_3) > > > > + return true; > > > > > > This is a bit of a nit, but I think it would be more consistent to use > > > has_cpuid_feature() here instead of __read_sysreg_by_encoding(), similarly > > > to how we handle kpti in unmap_kernel_at_el0() (which also has both an > > > ID register field and a list of MIDRs). > > > > force_pte_mapping required by map_mem(during early boot) needs > > cpu_supports_bbml3 check and cpu features/capabilities are not > > initialized by that time. Should i add a comment there to clarify this ? > > It looks to me like has_cpuid_feature() will call > __read_sysreg_by_encoding() under the hood for SCOPE_LOCAL_CPU. > > What am I missing? Below is my understanding. Correct me if i am wrong. has_cpuid_feature depends on struct arm64_cpu_capabilities *entry. Inorder to derive *entry from a capability ID, cpucap_ptrs should be in initialized state and that wont be the case when force_pte_mapping invokes cpu_supports_bbml3. > > Will